7. Consider the fragment of RISC-V assembly code belowsdx29, 12(x16)x29, 8(x16)х17, х15, х14Idsubbeqzaddx17, labelх15, х11, х14х15, х30, х14х2, х3, -1subaddi//implements x2 = x3 - 1addX2, х2, х5Suppose we modify the pipeline so that it has only one memory (that handles bothinstructions and data). In this case there will be structural hazard every time a program needsto fetch an instruction during the same cycle in which another instruction access the data.How many stall cycles are introduced in the code due to structural hazards?--Ans:

x29, 12(x16) x29, 8(x16) х17, х15, х14 x17, label х15, х11, х14 ub zba d ub ddi d х15, х30, х14 х2, х3, -1 //implements x2 = x3 - 1 х2, х2, х5 uppose we modify the pipeline so that it has only one memory (that structions and data). In this case there will be structural hazard every time a fetch an instruction during the same cycle in which another instruction acc

x29, 12(x16) x29, 8(x16) х17, х15, х14 x17, label х15, х11, х14 ub zba d ub ddi d х15, х30, х14 х2, х3, -1 //implements x2 = x3 - 1 х2, х2, х5 uppose we modify the pipeline so that it has only one memory (that structions and data). In this case there will be structural hazard every time a fetch an instruction during the same cycle in which another instruction acc

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Suppose pep/8 contains following four hexadecimal values: A= 19AC, X=FE20, Mem[OA3F]=FFOO, Mem[0A41]=103D If it has these values before running instruction C9OA3F, what are the values after running the instruction? Match the correct values for register A, register X, Mem[OA3F], and Mem[OA41]. 1. FF00 Mem[OA41] = 2. АС19 Mem[OAЗF] - 3. FE20 4. 103D 5. FEFE A 6. FD20 > > > >
9. Assuming that SP=2236H, AX=FFD4H, BX=8875H, and CX39812H, show the contents of the stack as each of the following instructions is executed: PUSH AX PUSH BX PUSH CX a. SP= 2233H Ob. SP= 2230H Oc. PS= 2242H
Q14. When pushing aregisterpair to thestack: a- SPregister gets decremented by 2. b- SP register gets incremented by 2. C- SP register gets decremented by 1. d- SP register gets incremented by 1. e- None of the above. Q15. Toexchange contents of DE & BC register pairusing the stack, we should: a- Push D followed by Push B then pop B followed by pop D. boPush D followed by Push E then pop B followed by pop D. c- Push B followed by Push D then pop B followed by pop D. d- Push C followed by Push B then pop B followed by pop E. e- None of the above. Q16. WR & RD pins are active low output from the CPU: a- When RD pin is 0, it means data bus is going to be output form the CPU. b- When WR pin is 0, it means data bus is going to be output form the CPU. &: Neither WR & RD can together be 0 at any time. d- Neither WR & RD can together be 0 at any time. e- None of the above. Q17. Subroutine: a- is called by CALL instruction. b- Can have another subroutine called from inside. C- Require RET…
one Mil Q#1: Consider the instruction: add $2, $1, $3 What registers will be written and what registers will be read to execute this instruction? Registers to be written Registers to be read Q#2: Since we only support the add instruction, we don't care much for opcodes and funct codes and shamts. Therefore, suppose our programs are given to the processor as three inputs RD, RS, and RT. Each instruction executes within 1 clock periods Translate the following program to the RW, RS, RT inputs (in binary). clock period RD RS 1 2 3 4 RS RT Program add $2, $1, $3 add $0, $0, $1 add $1, $2, $2 add $1, $1, $1 Q#3: Design the single-cycle cessor datapath (only ID, EX and WB stages) using the mong different components. following datapath components.rly s the number of bits to be transferred in each data line and data bus connectio RD cik Registers RA RB RW BusA RegWrite Bus8 Bus W ALU zero ALU result overflow RT ALUOP
Consider following assembly-language program: 11: Iw R1, 45(R2) 12: add R7, R1, R5 13: sub R8, R1, R6 14: or R9, R5, R1 15: bgtz R7, target 16: add R10, R8, R5 17: xor R2, R3, R4 18: sub R12, R10, R10 Using the given labels i.e. 1, identify all types of dependence with the two instructions involved, which instruction is dependent and if there is one, name the storage location involved (register/memory). Example: "I8 is dependent on 16 through R10"
3 C language into LC-3 Assembly Language
PROBLEM 1 For sorting a set of items, we can employ one of these famous algorithms, merge- sort, heapsort, quicksort, and shell-sort. We can program in both Java and Python, and we have the choice of using three different computers with different instruction set architectures: x86, ARM, and MIPS. Regarding microarchitecture, for x86 we have two choices, and for ARM and MIPS we have three choices for each of them. How many choices we have to run a sort algorithm? (Draw diagram).
Consider the fragment of LEGv8 assembly below: Program1 STUR X16, [X6, #12] LDUR X16, [X6, #8] SUB X7, X5, X4 CBZ X7, Label ADD X5, X1, X4 SUB X5, X15, X4 Suppose we modify the pipeline so that it has only one memory (that handles both instructions and data). In this case, there will be a structural hazard every time a program needs to fetch an instruction during the same cycle in which another instruction accesses data. 1- Draw a pipeline diagram to show where the code above will stall. 2- In general, is it possible to reduce the number of stalls/ NOPs resulting from this structural hazard by reordering code (reordering the instructions)? 3- Must this structural hazard be handled in hardware? We have seen that data hazards can be eliminated by adding NOPs to the code. Can you do the same with this structural hazard? If so, explain how. If not, explain why not. 4- If we run the code above on a single-cycle computer, what kind of hazards are there? Student should write a justification…
19.Consider the following program. How many clock cycles required to execute the program in the pipelined implementation using stalling? (Concern the control hazard only.) * [Program) i rmov $0,%rax i rmov $0,%rcx 13. LOOP: стр %гсх,%гах je EXIT inc %rax jmp LOOP i7. EXIT: hlt i1. i2. 14. i5. 16. 9 10 11 12
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E In the following code block(Reference:Q11), you will a set of assembly instructions with corresponding line numbers (line numbers are for informational purpose only and they are not part of the source code). 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 mov edx, 5 dec ecx jmp LABEL1 mov eax, 1 LABEL1: mul edx jmp ecx mov edx, 0678h sub edx, eax jmp DWORD PTR [edx] neg ebx add ecx, ebx mov eax, 0 For each of the conditions/scenario listed below, indicate the corresponding line number (that cause or is associated with the condition/scenario). Enter 0 (Zero) if the condition is not caused by the block of code. 1) Memory indirect jump: type your answer... type your answer... type your answer... type your answer... 2) Register indirect jump: 3) Relative short jump: type your answer... 5) Two's complement type your answer... 4) Relative near jump: 6) Unreachable code