Consider a pipeline processor with 5 stages S1 to S5. We want to execute the following loops: while(i ≤ 1) {11, 12, 13, 14) where i = 0. Time(ns) taken by the instruction 11 to 14 for stages S1 to S5 are given below: S1 S2 S3 S4 S5 11 1 1 2 1 1 12 1 2 1 1 1 13 1 2 2 1 1 14 2 1 2 1 1 The output of 14 will be available after

Consider a pipeline processor with 5 stages S1 to S5. We want to execute the following loops: while(i ≤ 1) {11, 12, 13, 14) where i = 0. Time(ns) taken by the instruction 11 to 14 for stages S1 to S5 are given below: S1 S2 S3 S4 S5 11 1 1 2 1 1 12 1 2 1 1 1 13 1 2 2 1 1 14 2 1 2 1 1 The output of 14 will be available after

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Consider two different implementations, 1 and 12, of the same instruction set. There are three classes of instructions (A, B, and C) in the instruction set. I1 has a clock rate of 6GHZ, and 12 has a clock rate of 3GHZ. The average number of cycles for each instruction class on 1 and 12 is given in the following table: CPI on 12 C1 Usage C2 Usage Class CPI on 11 C3 Usage A 2. 40% 40% 50% 40% 20% 25% 5 20% 40% 25% The table also contains a summary of average proportion of instruction classes generated by three different compilers. C1 is a compiler produced by the makers of 1, C2 is produced by the makers of 12, and the other compiler is a third-party product. Assume that each compiler uses the same number of instructions for a given program but that the instruction mix is as described in the table. Using C1 on both 1 and 12, how much faster can the makers of 1 claim 1 is compared to 12? Using C2, how much faster can the makers of 12 claim that 12 is compared to 1?
In some instruction sets, call and return instructions make use of a RR register to hold the return address rather than doing so on the stack. Show how the code in the above problem should be changed if call and return instructions used a RR register for return addresses rather than the stack. Don't change the program's function. 500 MOV R1, X 501 MOV R2, Y 502 MOV R3, Z 503 PUSH R1 504 CALL 550 505 POP R3 506 CALL 560 507 HALT · · 550 PUSH R2 551 CALL 560 552 POP R2 553 RET · · 560 PUSH R3 561 PUSH R1 562 POP R2 563 POP R1 564 RET
What is the physical address of this instruction Source operand of MOV BL, [SI + BP - 9H], If you know that (ES) = 1AOOH , %3D (DS) = 4200H , (SS) = DOOOH , (BX) = 0200H %3D , (BP) = 1000H, (SP) = 1020H , (SI) = 0400H , %3D (DI) = 0300 H PA = E2503 H O PA = 424F7H PA = D13F7H O PA = 424F6H PA = 1D503H O
We have the following C function compiled to RISC-V RV321. The following assembly sequence is equivalent to the C code snippet, but an assembly instruction is missing. what should be XXXX to have an equivalent code? int fun(char a) { fcall(); return a ^ 0x50; } fun: sp, sp,-16 ra,12(sp) s2,8(sp) s2, a0 addi SW SW mv call XXX fcall ra,12(sp) 52,8(sp) lw lw addi sp,sp, 16 jr ra O xori x10,s2,51 xori a0,s2,51 O Another instruction xori a0,s0,80 xori x10,s2,80
Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speed up achieved in this pipelined processor is
one Mil Q#1: Consider the instruction: add $2, $1, $3 What registers will be written and what registers will be read to execute this instruction? Registers to be written Registers to be read Q#2: Since we only support the add instruction, we don't care much for opcodes and funct codes and shamts. Therefore, suppose our programs are given to the processor as three inputs RD, RS, and RT. Each instruction executes within 1 clock periods Translate the following program to the RW, RS, RT inputs (in binary). clock period RD RS 1 2 3 4 RS RT Program add $2, $1, $3 add $0, $0, $1 add $1, $2, $2 add $1, $1, $1 Q#3: Design the single-cycle cessor datapath (only ID, EX and WB stages) using the mong different components. following datapath components.rly s the number of bits to be transferred in each data line and data bus connectio RD cik Registers RA RB RW BusA RegWrite Bus8 Bus W ALU zero ALU result overflow RT ALUOP
We wish to execute a single LC-3 instruction that will subtract the decimal number 33 from R1 and put the result in R2. Can we do it? a. No, because the smallest number that fits 5 bits is -32b. No, because we don't have SUB instruction to subtractc. No, because the smallest number that fits 5 bits is -16d. Yes, we can do it with a single instruction.e. none of the above.
Orthogonality means that an instruction set has a "backup" instruction that can be used instead of any other instruction that gets the same result. You have to prove or disprove my assumption.
Algorithm A, Algorithm B, and Algorithm C perform the same task. On input of size n, Algorithm A executes 10500n instructions, Algorithm B performs 30n2 instructions, and Algorithm C executes the ceiling of (1/1024) * 2n instructions. Assume each instruction requires the same amount of time in each algorithm. Algorithm A is slower than Algorithm B when the size of the input is less than .... Algorithm A is slower than Algorithm C when the size of the input is less than .... Algorithm C is fastest of the three when the size of the input is less than ....
Determine the effective CPI, MIPS rate, and execution time for this program. Consider two different machines, with two different instruction sets, both of which have a clock rate of 200 MHz. The following measurements are recorded on the two machines running a given set of benchmark programs: Instruction Count (millions) Instruction Type Machine A Arithmetic and logic Load and store Branch Others Machine A Arithmetic and logic Load and store Branch Others 8424 10 9824 Cycles per Instruction 1343 1243 4 a. Determine the effective CPI, MIPS rate, and execution time for each machine. b. Comment on the results.
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E In the following code block(Reference:Q11), you will a set of assembly instructions with corresponding line numbers (line numbers are for informational purpose only and they are not part of the source code). 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 mov edx, 5 dec ecx jmp LABEL1 mov eax, 1 LABEL1: mul edx jmp ecx mov edx, 0678h sub edx, eax jmp DWORD PTR [edx] neg ebx add ecx, ebx mov eax, 0 For each of the conditions/scenario listed below, indicate the corresponding line number (that cause or is associated with the condition/scenario). Enter 0 (Zero) if the condition is not caused by the block of code. 1) Memory indirect jump: type your answer... type your answer... type your answer... type your answer... 2) Register indirect jump: 3) Relative short jump: type your answer... 5) Two's complement type your answer... 4) Relative near jump: 6) Unreachable code