Write the corresponding Mic-1 MAL instruction to implement the following IJVM assembly instructions using a minimum number of clock cycles: BIPUSH2 word: Pushes an unsigned 2-byte operand to the top of the stack.

Explain why it is not possible to use direct addressing in ARM7TDMI microprocessor. For each of the following instructions, identify the addressing modes and calculate the effective address. Assume that register r3 = 0xF000, register r4 = 0x02 and register r0=0xF0. (i) LDR (ii) LDRB (iii) STRB (iv) LDRH r3, [r4, r0] r0, [r3, r4, LSL #3] r4, [r3], r0, ASR #3 r0, [4], r3

An 'instruction fetch/read' results in three sets of numbers that go to the Registers Block as studied in class. These three numbers in the instruction represent bits 25-21 for 'Read Register 1', bits 20-16 for 'Read Register 2', and bits 15-11 for the 'Write Register'. What does the 5 bits width of each of these indicate? a. That the word is 15 bits long in this architecture b. That each word is 32 bits long c. That there are 32 registers that can be addressed in this architecture d. That there are 15 registers that can be addressed in this architecture

2. Consider the following instruction: beq $t0, $t1, 0xA010 What are the values of Control signals generated by the MIPS architecture to execute this instruction. Show with a chart and explain it all clearly. (You may draw a simplified datapath flow)

1. Translate the following instructions so each can be directly executed by vertical architecture without using and additional registers. a. TIR := NOT(AMASK) + AC; Goto 65 b. A:= B + C + NOT(A); If Z goto 15 2.Show the hexadecimal value for OP, R1 and R2 for each instruction you come up with for part a and b in the above question.

Write a single MIPS instruction to invert all the bits in the register $s0 and write the result of the inversion in register $s1

The NOR instruction is not part of the RISC-V instruction set because the samefunctionality can be implemented using existing instructions. Write a short assembly codesnippet that has the following functionality: s3 = s4 NOR s5. Use as few instructions aspossible. Write RISC-V assembly code for placing the following immediate constants inregister s7. Use a minimum number of instructions.a) 59b) -199c) 0xDDCBE289d) 0x11236BDF

Following is the memory map beginning from address 3C00H and increasing addresses to the right , all in hex : 33, 5F, 00, FF, DE, C1, BB, 5E, 77, 95, 8C, ... Write down the value of each register after executing each instruction: MOV SP, -50168 РOP ВХ