The system from which this memory dump was produced contains 4 blocks of cache, where each
block consists of 8 bytes. Assume that the following sequence of memory addresses takes place:
0x2C, 0x6D, 0x86, 0x29, 0xA5, 0x82, 0xA7, 0x68, 0x80, and 0x2B.
a) How many blocks of main memory are there?
b) Assuming a direct mapped cache:
i. Show the format for a main memory address assuming that the system uses direct mapped
cache. Specify field names and sizes.
ii. What does cache look like after the 10 memory accesses have taken place? Draw the cache
and show contents and tags.
iii. What is the hit rate for this cache on the given sequence of memory accesses?
c) Assuming a fully associative cache:
i. Show the format for a main memory address. Specify field names and sizes.
ii. Assuming that all cache blocks are initially empty, blocks are loaded into the first available
empty cache location, and cache uses a first-in, first-out replacement policy, what does cache
look like after the 10 memory accesses have taken place?
iii. What is the hit rate for this cache on the given sequences of memory accesses?
d) Assuming a 2-way set associative cache:
i. Show the format for a main memory address. Specify field names and sizes.
ii. What does cache look like after the 10 memory accesses have taken place?
iii. What is the hit ratio for this cache on the given sequence of memory accesses? iv. If a cache
hit retrieves a value in 5ns, and retrieving a value from main memory requires 25ns, what is
the average effective access time for this cache, assuming that all memory accesses exhibit
the same hit rate as the sequence of 10 given, and assuming that the system uses a
nonoverlapped (sequential) access strategy
A direct mapped cache consists of 8 blocks. Byte-addressable main memory contains 4K blocks of
8 bytes each. Access time for the cache is 22ns, and the time required to fill a cache slot from main
memory is 300ns. (This time allows us to determine that the block is missing and bring it into
cache.) Assume that a request is always started in parallel to both cache and to main memory (so if
it is not found in cache, we do not have to add this cache search time to the memory access). If a
block is missing from cache, the entire block is brought into the cache and the access is restarted.
Initially, the cache is empty.
a) Show the main memory address format that allows us to map addresses from main memory to
cache. Be sure to include the fields as well as their sizes.
b) Compute the hit ratio for a program that loops 4 times from addresses 0x0 to 0x43 in memory.
c) Compute the effective access time for this program
Consider a byte-addressable computer with 24-bit addresses, a cache capable of storing a total of
64KB of data, and blocks of 32 bytes. Show the format of a 24-bit memory address for:
a) direct mapped
b) associative
c) 4-way set associative
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- Assume the address format for a fully-associative cache is as follows: 6 bits 2 bits Tag Offset 8 bits Given the cache directory is as shown in the diagram below, indicate whether the memory reference Ox5E results in a cache hits or a miss. Tag valid Block 000 110110 001 000001 010 000010 011 000101 100 001000 1 101 100010 110 010111 111 110110 O Hit O Missarrow_forwardQuestion 4arrow_forwardA cache is organized as a 4 way set associative cache Each set's cache line consists of 4 words (meaning there are 16 bytes per line, for each set of the cache). Each set individually has one Valid bit, and one Dirty bit, for each line. The tag field of this cache is 8 bits wide. The address is 32 bits wide. Question 1a) What is the number of cache lines? Question 1b) What is the total number of 'memory bitcells' that are needed to design this cache (note, this includes the bitcells required for the tags, valid and dirty bits).arrow_forward
- QUESTION 2 Suppose a computer using direct mapped cache is using 216 (64K) bytes of byte-addressable main memory, and a cache size of 4096 bytes, where each cache block contains 256 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by cache, i.e. what are the length of the tag, block, and offset fields? c) Given memory address 2B9D (in hexadecimal format), which block in the cache will be searched? (What is that block's id?)arrow_forwardSuppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each block contains 64 bytes.Q.) To which cache block will the memory address 0x01D872 map?arrow_forwardThe low order 4 bits of the address indicate location in the cache line and the next 4 bits indicate which line in the cache should be used and the remaining bits of the address are used as the cache tag. If the following addresses are read in this order, indicate (circle or similar) each one that would result in a cache miss. 2A1220 2A122C B14408 B14428 2A122Carrow_forward
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