The MOS transistors in the differential pair are mismatched. The nominal value of (VGS − VTN) = 0.75 V. (a) What will be the offset voltage if the (W/L) ratios are mismatched by 5 percent? (b) If the threshold voltages are mismatched by 5 percent?(c) If the values of λ are mismatched by 5percent? (d) If the drain resistors are mismatched by 5 percent? (Remember, the offset voltage is the input voltage required to force the differential output voltage to be zero.)

4. Sketch typical output characteristics for an enhancement mode long- channel n-type MOSFET. Show the gate voltage (V2) increasing in linear steps (e.g. Vg = 1 V, 2 V, 3 V, 4 V). Indicate on the characteristics where the onset of the saturated drain current (lasat) occurs for each curve. Give this drain voltage (Va) in terms of threshold voltage (V:) and Vg. 5. Show the effect of channel length modulation on the curves in part (4). Explain why channel length modulation occurs and why it is more prominent in short gate-length devices than in long gate-length devices.

1. Given the circuit D, 7. a. Derive Kerit and Reriras a function of duty cycle and switching time, the maximum Kerit and minimum Rcrit- b. Derive an expression for the de conversion ratio VNg of the buck-boost converter operating in discontinuous conduction mode. c. For K= 0.1, plot VVg over the entire range 0SDS 1. d. Explain what happens to V at no load (R-co )?

IV. In the circuit with a silicon transistor, as shown in the +Vcc Figure, if Viegic = 3.6 V, Vcc = 10 V, VLED = 2.3 V, RE = 270 2, B = 200, 1. identify the type of transistor in use and label the three terminals in the figure. logic input 2. find the base current. 3. find the collector current. 4. find the collector-emitter voltage. RE