Pls help me with both parts or esle skip thanks i will rate The following activation function is:20.5A) LineartoB) LogsigC) SatlinsD) TansigOE) Satlin910NJBased on Boolean Logic, the element is:OA)(C)OB)OD)E)between 0% and 100% element of the set.0% or 100% element of the set.None of the choices.not related to membership function.10% or 90% element of the set.%65

The above questions are based on fuzzy logic.

the following activation function is: 10.5 OA) Linear B) B) Logsig O Satlins OD) Tansig E) Satlin 9 Q 10 NJ Based on Boolean Logic, the element is: OA) OB) C) D) E) between 0% and 100% element of the set. 0% or 100% element of the set. None of the choices. not related to membership function. 10% or 90% element of the set. Q Q %65 C

the following activation function is: 10.5 OA) Linear B) B) Logsig O Satlins OD) Tansig E) Satlin 9 Q 10 NJ Based on Boolean Logic, the element is: OA) OB) C) D) E) between 0% and 100% element of the set. 0% or 100% element of the set. None of the choices. not related to membership function. 10% or 90% element of the set. Q Q %65 C

Electric Motor Control

10th Edition

ISBN:9781133702818

Author:Herman

Publisher:Herman

Chapter22: Sequence Control

Section: Chapter Questions

Problem 6SQ: Draw a symbol for a solid-state logic element AND.

See similar textbooks

Similar questions

T: Answer thne f. questions: 1) The hexadecimal number ´Al' has the decimal value equivalent to (A) 80 (B) 161 (C) 100 (D) 101 2) The output of a logic gate is 0 when all its inputs are logic 1. The logic is either (A) a NAND or an EX-OR (B) an OR or an EX-NOR (C) an AND or an EX-OR (D) an NOR or an EX-NOR 3) The Gray code of the Binary number 1100111 is (A) 1011011 (B) 1010100 (C) 1001001 (D) 101101 4) When simplified with Boollean Algebra (a+b)(a+c) simplifies to (A) a (B) a+a(b+c) (C) a(1+bc) (D) a+bc 5) -31 is represented as a sign Binary number ( using Sign-magnitude form ) equal to (A) 00011111 (B) 10101001 (C) 01110010 (D) 00101101 6) The Binary number 110111 is equivalent to decimal number (A) 25 (B) 55 (C) 26 (D) 34 7) With 4 bit, what the range of decimal values if the number is 2's complement signed number. (A) -32 to +31 (B) -2 to +1 (C) -8 to +7 (D) None of these
Design a 3-bit counter that counts the following sequence: 7,5, 3. 1.0.7, 5. 3, 1, 0, 7. etc. Using the sequential design technique that starts from a state diagram, draw the state table. minimize the logic. and draw the final circuit. The outputs of logic circuit are 2 = Qo Q1. I, = Qo.Qi + Qo.Qi, Io = Qo.Q2, Cont2 = Qj Q2 Cont1 = Qu Q2. Cont0 = Q2 Qo.Q1. h = Qo.Qi + Qo.Q1, Io = Qo Qz Cont2 = Q, Q2 Contl = Qo Q2 Cont0 = Q2 Qo Qı Ij = Qo.Q, + Q».Qı, Io = Qo. Q2. Cont2 = Qj Q2. Contl = Qo.Q2. Cont) = Q2 L = Qo.Qı. I¡ = Q. Qj + Qu Q Io = Qv.Qz Comt2 = Q, Q, Contl = Q Q2 Cont0 = Q2 !! fefsto How much will be per-product cost and th
4- Draw the output waveform if the signal shown in Figure below is applied to inputs of J-K Flip-Flop. Q is initially Low. HIGH CLK- CLR nnnnnnn CLK PR CLR
a) Create a 4 Variable Karnaugh Map in paper by mapping 1’s for given standard SOP Boolean expression. After mapping , make relevant groups within Karnaugh Map by considering rules for making groups for 4 variable Karnaugh Map. After making relevant grouping , extract the minimum SOP expression by considering rules for extracting minimum SOP using Karnaugh Map. * Standard SOP: *Create Circuit Diagram using logic gates and logic converter in Multisim for given standard SOP and minimum SOP which you have solved. Do make sure that truth table for both expressions should evaluate same result.
This question is from the subject Digital Logic Design. Q2. Two Boolean functions are represented in the following truth table.a) Represent the function F1 and F2 in Some of Min-terms (SOM).b) Simplify both functions as Some of Products (SOP).
please draw a logic diagram with following description Two D flip-flops (DFF1 and DFF0): DFF1 stores Q1 DFF0 stores Q0 Combinational logic for D flip-flop inputs (D1 and D0): D1 = Q1 & power D0 = power & (Q1 ^ sensor) Output signals (A, B, C , and D): A = ~(Q1 | Q0) B = ~Q1 & Q0 C = Q1 & ~Q0 D = Q1 & Q0
Design a 4-bit arithmetic circuit, with two selection variables S1 and S0, that generates the arithmetic operations in the following table. Draw the logic diagram for a single bit stage. Note that B’ represents “Not B”. Draw the logic diagram for a single bit stag
parity generator design, construct and test a circuit that generates an even parity bit ffrom four messages bits . use XOR gates. adding one more XOR gate, expand the circuit so that it generates an odd parity bit also.
a) Design a single-digit decade counter that counts from 0 to 9 and repeats. The single-digit decade counter should be built by a cascaded synchronous binary counter (74LS163) and other basic logic gates. Simulate thecomplete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform.(Define the simulation timings for at least one full counting cycle from 0 to 9 and back to 0.)(Hint: Use the DigClock input from the SOURCE as shown below and setup the CLK ONTIME and OFFTIME accordingly for the clock source.)
Examine the circuit given below. Write the expression for outputs Q1, Q2, and Q. Clearly indicate which logic gate Q output is using Boolean Algebra and write the name of this logic gate.
c) d) Explain the different between sequential circuit and combinational circuit. a) Identify input conditions necessary in order to set, reset and toggle the JK flip flops in Figure Q3d(i) and Q3d(ii). Clock QUESTION 4 J K Q व Figure Q3d(i) Clock S R Clock Convert the SR flip-flop in Figure Q4a to behave like JK flip-flop. ā Figure Q4a a J K Q ā Figure Q3d(ii)
Problem Statement: You design a circuit of a decade counter that will count from 0-9 only. You will only be using the following: (a) Button – only 1 button will be used to trigger the counting. (b) Flip flop IC to used as counting circuit with 4 - BITS binary OUTPUT. (c) IC's for Decoding the Binary OUTPUT of Flip-flops to Decimal Output (d) 7- Segment Display to display the OUTPUT from 0-9. Block Diagram: 4 Bit Binary Flip-Flop 7-Segment Display Button Decoder Circuits Circuits