Suppose a computer system has a memory organization with only three levels of hierarchy, a cache, a main memory and a hard drive. Access times and miss rates are given in Table below. Now find the followings: Access Time Memory Unit Hit Rate (Cycles) Cache 90% Main memory 105 95.50% Hard drive 1,080,000 0% 1. Miss rate of the main memory. 2. Average memory access time. 3. For 1350 cache hits, find the number of total cache accesses while hit rate is given in Table 4. If number of hits are 1350 and cache hit rate is given in Table then how many times data has been provided from main memory?

QUESTION 9 1. If a given memory address for a byte addressable machine is found in a cache that uses a 128 byte cache line size, the least significant 8 bits in the memory address will be used to select the byte(s) in the cache line to work with. True False QUESTION 10 1. SRAM memory is used predominately in: C SRAM memory is used predominately in: C motherboard main memory C BIOS PROM memory C SD card memory devices C CPU on-chip cache memory

Consider a virtual memory system with the following characteristics for accessing memory: 1 nanosecond for a read operation with a hit in cache 5 nanoseconds for a read operation with a miss in cache 2 nanoseconds for a write operation with a hit in cache 10 nanoseconds for a write operation with a miss in cache The cache hit ratio is 0.9   If a sequence of instructions were executed: 100 instruction fetch operations, 60 memory operand read operations, and 40 memory operand write operations, what would be the average memory access time (in nanoseconds) in executing the sequence of instructions:

If random access memory (RAM) and cache memory (both of which are comprised of transistors), then what is the function of cache memory? Do we need several different forms of memory, or can we get by with only one?