Suppose a computer system has a memory organization with only three levels of hierarchy, a cache, a main memory and a hard drive. Access times and miss rates are given in Table below. Now find the followings: Access Time Memory Unit Hit Rate (Cycles) Cache 90% Main memory 105 95.50% Hard drive 1,080,000 0% 1. Miss rate of the main memory. 2. Average memory access time. 3. For 1350 cache hits, find the number of total cache accesses while hit rate is given in Table 4. If number of hits are 1350 and cache hit rate is given in Table then how many times data has been provided from main memory?

Suppose a computer system has a memory organization with only three levels of hierarchy, a cache, a main memory and a hard drive. Access times and miss rates are given in Table below. Now find the followings: Access Time Memory Unit Hit Rate (Cycles) Cache 90% Main memory 105 95.50% Hard drive 1,080,000 0% 1. Miss rate of the main memory. 2. Average memory access time. 3. For 1350 cache hits, find the number of total cache accesses while hit rate is given in Table 4. If number of hits are 1350 and cache hit rate is given in Table then how many times data has been provided from main memory?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

QUESTION 9 1. If a given memory address for a byte addressable machine is found in a cache that uses a 128 byte cache line size, the least significant 8 bits in the memory address will be used to select the byte(s) in the cache line to work with. True False QUESTION 10 1. SRAM memory is used predominately in: C SRAM memory is used predominately in: C motherboard main memory C BIOS PROM memory C SD card memory devices C CPU on-chip cache memory
Consider a virtual memory system with the following characteristics for accessing memory: 1 nanosecond for a read operation with a hit in cache 5 nanoseconds for a read operation with a miss in cache 2 nanoseconds for a write operation with a hit in cache 10 nanoseconds for a write operation with a miss in cache The cache hit ratio is 0.9 If a sequence of instructions were executed: 100 instruction fetch operations, 60 memory operand read operations, and 40 memory operand write operations, what would be the average memory access time (in nanoseconds) in executing the sequence of instructions:
If random access memory (RAM) and cache memory (both of which are comprised of transistors), then what is the function of cache memory? Do we need several different forms of memory, or can we get by with only one?
Calculate the CPU execution time (expressed in milliseconds) of a program with 10 million instructions on a 2.5 GHz CPU with the following basic instruction-type breakdowns and CPIs: Arithmetic: 60%, CPI = 2 Load & Store (assuming perfect caches): 25%, CPI = 5 Branching: 15%, CPI = 3 In addition, you are told that the overall cache miss rate for instructions is 1%, the overall cache miss rate for data is 3%, and the cache miss penalty is 100 cycles. You can ignore the hit time (consider it zero).
Consider the execution of a program that results in the execution of 8 million instructions on a 400-MHz processor. The program consists of four major types of instructions. The instruction mix and the CPI for each instruction type are given below. What is the program execution time in the second? Instruction Type Arithmetic and logic Load/store with cache hit Branch Floating-point arithmetic operation Execution Time: sec CPI 3 4 3 9 Instruction Mix (%) 60 20 12 8
Please solve quickly, computer architecture material, we look at 6 points and in two ways
A memory hierarchy contains a single cache with a miss rate of 2% that holds both instructions and data. The miss penalty to access main memory is 100 cycles. 15% of the instructions are jumps, 20% are stores, 20% are loads (30% have values used in the next instruction), 10% are branches (taken 20% of the time), and 35% are ALU instructions. Jumps and branches are determined in the ID stage. What is the base CPI, and what is the effective CPI?
Let (BX)=100H, DI=200H, DS 1200H, SI= F002H, AX= 0105H, and the following memory content. what is the content of SI after executing the MOV SI, [DI+BX+7H] ?instructions Memory Memory address content 12300 11 12301 AA 12302 EF 12303 80 12304 47 12305 8D 12306 5A 12307 92 12308 C5 SI = C592H O SI-F002H O SI = 92C5HO SI = EF80HO SI = 80EFHO If BL=XXH and make CMP BL,BL the sign and zero flags will be SF=1, ZF=0 O depend on the value on the BL register O SF=0, ZF=1 O SF=ZF=0 O SF=ZF=1 O