Question a) (For the input waveforms in Figure 1, design a simplified logic circuit that will generate the output waveform. (Hint: You can use K-map) Inputs B Output X Figure 1: Input/output characteristics of the logic circuit b) Design a two-bit full adder circuit and verify its properties by plotting the output for input waveforms shown in Figure 2. Question (a) Design a circuit using D flip-flops that can be used to divide the clock frequency by 16. (b) Draw the input and output waveforms for each stage to the circuit designed in part (a).

2.31 For the timing diagram in Figure P2.3, synthesis the function f(x1, x2,x3) in the simplest sum-of-products form. X2 Time Figure P2.3 A timing diagram representing a logic function

In motor control of train, IGBT control AC motor save more energy than GTO due to less switching loss. State THREE more reasons why IGBT use in motor control has many advantages over GTO. If one of the freewheeling diode in your single phase inverter in above settings has reverse recovery failure. Describe what would happen to the circuit.

What is a TTL circuit? What are their main characteristics? (Input voltage and current, output voltage and current, Vcc, …)

Y=f(A,B,C)=(0,4,5)+don't care(2)

Construct the state diagram...

Q5 (a) Discuss, the major dıfferences between ticld programmable gatc arrays (FPGAS) and programmable logie devices (PLDS. where an FPGA may be approprate in a streamıng TV system. Simple multiplexers can be used to mimic a number of two-input logic functions by appropriate mapping of nputs X X, and SEL Show how the multiplexer shown in figure Q5a can be used to perform the function F= AOB (b) SEL Figure Q5a Figure Q5b (over) shows the schematic of a Xilinx 3000 sennes logic cell M Label the configuration bits of the various multiplexers n the celL with zeroed configuration bits selecting the topmost input to each multuplexer. Each multiplexer has -2 ns, the combinatorial loge block is guaranteed to have WS7 ns, and the D-type flip-flops have t4 ns and r 1 ns (c) We wish to construct a two-bit counter from this logie cell. where Q, and Q are the high and low order outputs of the counter, CLK is the clock signal, AR is an asynchronous reset signal, EN enables the counter, and LD allows…

Implement the logic circuit in Figure 2 using only NAND gate A B C X

1. Design an Excess-3 (Ex-3) checker circuit for an input of 4-bits. (the output is logic 1 if the input is a valid Excess-3 and is 0 otherwise).

Q5. A general analysis of the switch-mode inverter shown in the figure below is to be done. The switching frequency f,, which is also the frequency of the triangular signal is 1450 Hz. The de voltage, Va, is 600 V. Output voltage is sinusoidal voltage with a frequency equal to 50 Hz. TA ADA. TA- ADA- VAN (Figure 8-4 on page 203 from Mohan's Book) a. Find the frequency modulation ratio, mr. b. Why the frequency modulation is chosen as an integer? c. Calculate the output voltage (rms value of first harmonic), when the amplitude modulation ratio, m., is equal to 0.8. d. Compute the rms values of the 5 most dominant harmonics of v4o at m,=0.8. e. Also indicate the frequencies at these harmonics you have found in part d appear.