Question 1 (> For the first 14 questions, use the MIPS assembly code: SW $22, 40($24) AND $8, $17, $18 ADDI $20, $12, 5 OR $16, $10, $11 Each register contains an initial value of decimal 100 plus its register number. (e.g. register $8 contains 108, register $22 contains 122, etc), The code begins running on a 5-stage MIPS pipelined processor with SW starting in cycle 1. Diagram the instructions within a pipeline diagram to determine which stage each instruction will be in during each cycle. Then answer the next 14 questions, During cycle 3, which instruction will use values from the IF/ID pipeline register? Question 2 During cycle 4, which instruction will use values from the ID/EX pipeline register? Question 3 During cycle 4, what decimal register number will be obtained from ID/EX.RegisterRs? Question 4 During cycle 4, which instruction will use values from the EX/MEM pipeline register? Question 5 ( During cycle 4, what decimal value is obtained from EX/MEM.ALUresult ?

2. Memory contents (in hexadecimal) are 0005, 0001, 0123 for addresses 000 to 002, then 2002, 1000, 7800, F400 for addresses 80A through 80D. AC starts with value 0F24, PC has the value 80A, and AR has the value 4F5. Starting with time-step T0, describe what happens until the next TO. Make sure to indicate any updated register values as they happen. (Assume R= 0.) Refer to table 5.6 from Mano's textbook. F24 1 AR

I  need proper explanation

Question 5 Write MIPS assembly program to print integer number from 1 to 100. Each number should be printed in a separate line. Note: • The system call code is 1 for printing an integer and is 11 for printing a character. For both cases, the argument (i.e., data to print) should be stored in $a0. • The character of "new line" is "\n. • You can use instruction li $r "\n' to load the character "\n' into a register $r. Edit View Insert Format Tools Table 12pt v Paragraph v B IUA vev T? v :

1. If the AL register is storing the binary number 10010010, what will be the contents of the BX register in binary after the instruction "movzx bx, al"? What would be the contents of the BX register in binary if this instruction is performed instead: "movsx bx, al"? What happens if you set ECX to 0 before beginning a loop? Is LOOP an unconditional or conditional transfer instruction?

How many trap service routines could theoretically be created for the LC-3, given the format of the TRAP instruction? (hint: how many bits are used for the trap vector?) 8 64 O 256 О 16к 32

Suppose that we are developing a new version of the AMD Barcelona proces- sor with a 4 GHz clock rate. We have added some additional instructions to the instruction set in such a way that the number of instructions has been reduced by 15% from the values shown for each benchmark in Exercise 1.12. The execution times obtained are shown in the following table. a. Name Execution Time (seconds) Reference Time (seconds) bzip2 700 9650 SPECratio 13.7 1.13.2 [10] In general, these CPI values are larger than those obtained in previous exercises for the same benchmarks. This is due mainly to the clock rate used in both cases, 3 GHz and 4 GHz. Determine whether the increase in the CPI is similar to that of the clock rate. If they are dissimilar, why?