I need the answer as soon as possible • Q7Consider a machine with a byte addressable main memory of 216 bytes and block size of 8 bytes.Assume that a direct mapped cache consisting of 32 lines is used with this machine.a. How is a 16-bit memory address divided into tag, line number, and byte number?b. Into what line would bytes with each of the following addresses be stored?0001 0001 0001 10111100 0011 0011010o1101 0000 0001 11011010 1010 1010 1010c. Suppose the byte with address 0001 10100001 1010 is stored in the cache. What are theaddresses of the other bytes stored along with it?d. How many total bytes of memory can be stored in the cache?e. Why is the tag also stored in the cache?• Q8State the difference between an 1/0 address register and an 1/0 buffer register.• Q9List and briefly define the QPl protocol layers.• Q10List and briefly define the PCle protocol layers.

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• Q7 Consider a machine with a byte addressable main memory of 216 bytes and block size of 8 bytes. Assume that a direct mapped cache consisting of 32 lines is used with this machine. a. How is a 16-bit memory address divided into tag, line number, and byte number? b. Into what line would bytes with each of the following addresses be stored? 0001 0001 0001 1011 1100 0011 00110100 1101 0000 0001 1101 1010 1010 1010 101o c. Suppose the byte with address 0001 1010o0001 1010 is stored in the cache. What are the addresses of the other bytes stored along with it? d. How many total bytes of memory can be stored in the cache? e. Why is the tag also stored in the cache? • Q8 State the difference between an /0 address register and an 1/0 buffer register. • Q9 List and briefly define the QPI protocol layers. Q10 List and briefly define the PCle protocol layers.

• Q7 Consider a machine with a byte addressable main memory of 216 bytes and block size of 8 bytes. Assume that a direct mapped cache consisting of 32 lines is used with this machine. a. How is a 16-bit memory address divided into tag, line number, and byte number? b. Into what line would bytes with each of the following addresses be stored? 0001 0001 0001 1011 1100 0011 00110100 1101 0000 0001 1101 1010 1010 1010 101o c. Suppose the byte with address 0001 1010o0001 1010 is stored in the cache. What are the addresses of the other bytes stored along with it? d. How many total bytes of memory can be stored in the cache? e. Why is the tag also stored in the cache? • Q8 State the difference between an /0 address register and an 1/0 buffer register. • Q9 List and briefly define the QPI protocol layers. Q10 List and briefly define the PCle protocol layers.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter11: Operating Systems

Section: Chapter Questions

Problem 21VE

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