Q2. (a) For a 64 Kbit symmetric memory IC, determine the number of transistors needed to implement a tree type column decoder circuit. If a bit-line type column decoder is now used instead, how many transistors will be correspondingly required? (b) A symmetric DRAM IC is to be designed. Due to the fabrication process in practice, each memory cell will have a cell capacitance of 1.05 fF and poly-silicon cell resistances of 100 ohm. It is a requirement that the row line delay to be not more than 15 nsec. What could be the largest capacity, in number of bits stored, of the fabricated memory IC? Assume no row line partition has been carried out. Specify units at every stage of your computation. What would be the capacity if the row lines are partitioned into two sections each independently driven by the row decoder circuit?

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Hi! Please may I have the solution to this question 2 in a step by step form. Thank you very much.

Q2.
(a) For a 64 Kbit symmetric memory IC, determine the number of transistors
needed to implement a tree type column decoder circuit. If a bit-line type
column decoder is now used instead, how many transistors will be
correspondingly required?
(b) A symmetric DRAM IC is to be designed. Due to the fabrication process in
practice, each memory cell will have a cell capacitance of 1.05 fF and poly-silicon
cell resistances of 100 ohm. It is a requirement that the row line delay to be not
more than 15 nsec. What could be the largest capacity, in number of bits stored,
of the fabricated memory IC? Assume no row line partition has been carried out.
Specify units at every stage of your computation.
What would be the capacity if the row lines are partitioned into two sections
each independently driven by the row decoder circuit?
Transcribed Image Text:Q2. (a) For a 64 Kbit symmetric memory IC, determine the number of transistors needed to implement a tree type column decoder circuit. If a bit-line type column decoder is now used instead, how many transistors will be correspondingly required? (b) A symmetric DRAM IC is to be designed. Due to the fabrication process in practice, each memory cell will have a cell capacitance of 1.05 fF and poly-silicon cell resistances of 100 ohm. It is a requirement that the row line delay to be not more than 15 nsec. What could be the largest capacity, in number of bits stored, of the fabricated memory IC? Assume no row line partition has been carried out. Specify units at every stage of your computation. What would be the capacity if the row lines are partitioned into two sections each independently driven by the row decoder circuit?
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