Q1. Timing analysis (Graded for completion) CLK CLK CLK Given the circuit, each two-input XOR gate has a propagation delay of 80 ps and a contamination delay of 40 ps. Each flip-flop has a setup time of 80 ps, a hold time of 50 ps, a clock-to-Q propagation delay of 100 ps, and a clock-to-Q contamination delay of 70 ps. (a) If there is no clock skew, what is the maximum operating frequency of the circuit?

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