A D flip-flop has a hold time of three ns, a setup time of five ns, and a propagation delay from the rising edge of the clock to the change in flip- flop output in the range of 6 to 12 ns. A comparator (combinational circuit) unit delay is in the range of (.... You have to calculate it based on using 2- input NAND gates for the implementation and response time per every NAND gate is one ns). X Comparator Z-X Z CLK Flip-Flop a) What is the minimum clock period for prover operation of the circuit above? b) What is the earliest time after the rising clock edge at which X is allowed to change?

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