Q1) Name the addressing mode for the following instructions; a) MOV DX, AX b) MOV AX, [DI+SP] c) MOV AL, [BX] d) ADD DX, [123FH]
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![Q1) Name the addressing mode for the following instructions;
a) MOV DX, AX
b) MOV AX, [DI+SP]
c) MOV AL, [BX]
d) ADD DX, [123FH]
e) MOV CL, 5DH](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F12ca9eab-9680-4750-9560-a78c1c64a059%2F26f83197-a2e3-4d9e-a071-6f36eda31c20%2Fztycr_processed.jpeg&w=3840&q=75)
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- Q2) Convert to decimal number: 1) The hexadecimal number (FD45) 2) The octal number (7024) 3) The EX-3 (11001010.00110110) 4) The number of base 9 (8301)A 12-bit ADC unit has an input voltage range of -ve 5to +ve 5 VDC. What is the minimum difference in voltage required by an analogue signal for the digitally converted value to reflect that change(resolution)? 0.0012V DC b. None of all 0.083V DC C. 0.0024V DC 4(c) Figure Q3(c)(i) shows a register and Figure Q3(c)(ii) shows the input waveforms (CLOCK and Data in) to the circuit. A1 A9 A10 A2 Function generator A3 A11 A12 AS A13 A6 A14 A7 A15 Data in Bop.7) ip.r 82p.7) Logic analyser U1 U2 U3 U4 UO 6. 1. 6 1 6 INVERTER 3 CLK 3 CLK oCLK CLK 5 K K 5 K K 4027 Clock Function generator Figure Q3(c)(i) (i) Determine the type of register as shown in Figure Q3(c)(i).
- Adocs.google.com is a logic switch that select information from one of the input line and directs it to a single line Encoder Decoder Adder Multiplexer Binary to octal can be implemented used 3-8 De-Multiplexer Multiplexer Decoder Encoder System base 12 include numbers from ... to .... 1-B 1-C 1-12 1-11 ۹:۰۳ FWhat is the hexadecimal value stored in Register A after the following assembler has executed? LDA #0x71 NOTA NOTA LDR B,#0x71 ADC A,B LDR B,#0xEB ADC A,B NOTA LDR B,#0xD5 ADC A,B LDR B,#0x53 SBC A,B LDR B,#0x19 SBC A,B LDR B,#0x5E SBC A,B1.Without using the MUL instruction, give instructions that multiply register r4 by: a)128 b)253
- 1. In the following diagram, you have the architecture of the Intel 8086 questions: Briefly following microprocessor. [CO1/UNDERSTAND] To memory and Input/ Output answer the BIU 6. 5. 4 3. 2 Σ 6-Byte pre-fetch PA Seg X 10H + offset CS SS DS ES IP queue Control Unit EU AH AL AX General BH BL -BX -CX -DX Purpose Registers CH CL DH ALU DL SP ВР SI DI Operands Flags Block Diagram of 8086 Microprocessor Electronics Desk a)Why is the architecture of 8086 divided into two parts? How can the two units enhance the total system performance? b)How many registers are there inside Intel 8086? What is the purpose of segment registers and general-purpose registers? Mention the names also.Q1. Show the implementation of 4 bit binary to gray code (shown in below table) converter using either EPROM or PLA. In Gray code only one bit changes at a time. Binary Gray code Decimal equivalent 0000 0000 1 0001 0001 0010 0011 3 0011 0010 4 0100 0110 5 0101 0111 6. 0110 0101 7 0111 0100 8. 1000 1100 1001 1101 10 1010 1111 11 1011 1110 12 1100 1010 13 1101 1011 14 1110 1001 15 1111 1000Fill the register AL with the bit 3 of AH, i.., emu 8086 If b3 of AH=0 then AL must be 00H If b3 of AH=1 then AL must be FFH
- 1. Use multiplexer IC's to design a combinational circuit with 3 inputs x,y, and z and three outputs A,B, and C. When the binary input is 0,1,2 or 3 the binary output is two greater than the input. When the binary input is 4,5,6, or 7 the output is three less than the input.Interface an input port 74LS245 to read the status of switches SW1 to SW8. The switches when shorted input a ‘1’ else input a ‘0’ to the microprocessors system. Store the statusi inregister BL. The address of the port is 0740H.in Intel 8086 microprocessor, the memory address for the code segment 771Fh and offset 3584 h is O 7A774 3CF5F О АСАЗО OACA3 in Intel 8086 microprocessor, the memory address for the code segment 3021 h and offset 21D7h is 323E7 51F80 051F8 24D91