Q.7 The following sequences of bits (right-most bit first) appear on the inputs to a 4-bit parallel adder. Determine the resulting sequence of bits on each sum output. Al 1010 A2 1100 A3 0101 solve Q7 A4 1101 S B1 1001 B2 1011 B3 0000 B4 0001

add 25 and -20 (using 8-bit numbers) 8 and -19 (using 8-bit numbers)

Design a 2-bit binary adder with carry. Your circuit should allow for two 2-bit binary input (a1a0 &b1b0) through switches and display the results of the addition in decimal format using the 7-segmentdisplay.

Electrical Engineering Verilog Design N-bit binary counter which counts the number from 0 to 2N-1. After reaching to maximum count i.e. 2N-1, it again starts the count from 0. i. Write the description of the counter in Verilog ii. Generate the design from the listing ii. Produce the waveforms of the counter

Please do this, urgently needed.

1. Gray code to Binary converter: Gray code is one of the codes used in digital systems. It has the advantage over binary numbers that only one bit in the code word changes when going from one number to the next. (See Table 1). Design a combinational circuit with 4 inputs and 4 outputs that converts a four- bit gray code number into an equivalent four-bit Binary number. Use Karnaugh map technique for simplification. Use LogicWorks for pre-lab demonstrations. Select the library "7400dev.clf* in the Parts Palette and then select the XOR chip 74-86. This would give you a set of 4 XOR's as shown in Fig. 1, just like the hardware chip 74-86. You could use as many as needed from these XOR gates in your design. Get back to ALL LIBRARIES and select switches for the inputs and Binary Probes as indicators of the outputs. Verify your design in the pre-Lab. During the Lab construct the circuit and verify its operations.

Complete the Hamming code below for the given 4-bit hex values. Insert the ODD parity bits into positions 1, 2, and 4. For this problem, P means POSITION, not parity. The parity bit in P1 checks bits P1, P3, P5, and P7. The parity bit in P2 checks bits P2, P3, P6, and P7. The parity bit in P4 checks bits P4, P5, P6, and P7. Hex 0: 7: A: P1 P2 P3 0 P4 P5 0 1 ? P6 0 1 ? P7 0 1 ?

Digital logic design Solve it with drawing and simulation lab I need them both to have the full solution. And thanks Design counter that counts from 00 to 59, using the IC 74LS90 ripple counter and use two 7 segment display to display the result count. You can also use 7447 binary to 7-segment Display Decoder.

5. In the circuit implementation of an 8-bit adder, explain why the carry bit connection of the least- significant bit is connected to ground. Explain in words what values for A, B, C, D, E will cause a 1 to appear at point X. The circuit below uses a 5-input AND gate. Draw the equivalent circuit using only 2-input gates.

For a 4-bit parallel adder, if the carry-in is connected to a logical HIGH, the result is O a. The carry-out is ignored b. The same as if the carry-in is tied LOW since / the least significant carry-in is ignored O C. A one will be added to the final result o d. That carry-out will always be HIGH