Q-10: Assume byte-addressable main memory has address size of 24 bits. For a 2-way-set-associative - mapped cache design, the following bits of the address are used to access the cache. Tag: 13 bits, set: 7 bits and Word: 4 bits (i) What is the cache line size in bytes? (ii) How many entries does the cache have? (iii) What is the ratio between total bits required for such a cache implementation over the data storage bits? Starting from power on, the following byte-addressed cache references are recorded.Addresses: 04 32 64 128 256 512 1024 2014 O 4 32 (iv) How many blocks are replaced?(v) What is the hit ratio? (vi) Show the state of cache memory at the end (the cache lines containing blocks of main memory)

Q-10: Assume byte-addressable main memory has address size of 24 bits. For a 2-way-set-associative - mapped cache design, the following bits of the address are used to access the cache. Tag: 13 bits, set: 7 bits and Word: 4 bits (i) What is the cache line size in bytes? (ii) How many entries does the cache have? (iii) What is the ratio between total bits required for such a cache implementation over the data storage bits? Starting from power on, the following byte-addressed cache references are recorded.Addresses: 04 32 64 128 256 512 1024 2014 O 4 32 (iv) How many blocks are replaced?(v) What is the hit ratio? (vi) Show the state of cache memory at the end (the cache lines containing blocks of main memory)

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter6: System Integration And Performance

Section: Chapter Questions

Problem 22VE

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