Problems: 1. Use open collector inverters to implement the following logic expressions: (a) X = ABC (b) X= ABCD (c) X = ABCDEF
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- The inverter 74 ALSO4 has the following specifications IOHmax = -0.4 mA, IoLmax = 8 MA, IiHmax = 20 mA, IiLmax = -0.1 mA, Find the fan out.5- Determine an alternative method for implement the full-adder. Hint: Write the expressions of the circuit and simplify using icarnaugh map.Then implement using AND-OR gates. 6- Design a logic cct using NAND gate and convert BCD code to Excess-3code.VS Inverter.
- 4. CMOS Logic Gate The PUN of a CMOS Logic Gate is shown below Vdd Q1 B- Q2 c -dPQ3 B-dCa5 Q6 D Y (a) Determine Y from the PUN. Express your answer in Sum-of-Product form. (b) Sketch the PDN of this CMOS logic gate. (c) Transistor sizing. If we set Peg = 5 for this CMOS logic gate, find W's for Q1 through Q7 if L is set at 0.25µm.An inverter with a resistive load, VDD = 3.3 V, P = 0.1 mW, VL = 0.2 V, K'n = 60 UA/V2 and VT N = 0.75 V. The value of (W/L)S is:Below is an example of an NMOS logic circuit. For all of the MOSFETs in the circuit below, assume V = 1 V and k = 50 mA/V². th R₂ = 5600 R₁ = 4700 M3 Ao M₁ M₂ a. Indicate and verify the state of each MOSFET and V for the following input 0 combinations. Fill-out the table below for each assumed state of the MOSFET for every input combination. Use R approximation for linear operation and three significant ds(on) figures for the voltages. Example: M1 is assumed to be in saturation. If Vgs = 2 V, Vds = 4V, Vds > Vgs - Vth 4>2-1 4> 1 (ok) Vgs > Vth (2>1) A B M1 state M2 state M3 state V OV OV 5 V OV b. What kind of logic circuit is implemented in the circuit above? 5V www. V₂ 0
- Q/ Totem-pole outputs cannot be connected together, why? How is this condition treated? 2- Design TTL inverter gate, Explain the usefulness of a diode in a circuitQ2 A) Starting from Ex-OR (SOP) expression: a- develop Ex-NOR (SOP) expression. A O A=.... b- Find AO 1=..., B) Draw the logic circuit diagram for 4x1 Multiplexer.We want to design a circuit to detect prime numbers.The input of the circuit is a 4-bit binary number and the output is a single bit and should show one when the number is prime and zero otherwise.B. Implement the circuit using a 4× 1 multiplexer and combinational logic gates.C. Implement the circuit using only one decoder and one OR gate. What is the size of the decoder you use?
- (b) For a gated S-R latch. determine the Q output for the inputs in the following Figure. Show it in proper relation to the enable input, also draw the input waveforms on your answer script. Assume that Q starts LOW. EN S R Minimize the combinational logic circuit in the following figure using Karnaugh's map only. Inverters for the complemented variables are not shown. Q2.Inverters create an ac voltage when only a dc voltage source is available. Select one: O a. True O b. None of the above O c. False Jump to...6. i) For the circuit shown in Figure Q16, Find the logic functions of X and Y Figure Q1 ii) Simplify X and Y using Boolean algebra. hp ort delete