please help me code a working testbench with comments
This is a HDL code for the state machine below, please help me code a working testbench with comments for better understanding for this structural module. The diagrams provided are the state diagrams and logic circuit diagrams for this circuit/module. I will rate 5 star for this pls tq
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module dsd_assignment_structural_s ( input clk, x, clr, //setting input clock, x and clear/reset output [2:0] Q, Qbar, //setting output Q, Qbar and Z output z);
wire j0, j1, j2, j3, j4, j5, j6, j7, j8, j9, j10, j11, dclk; //wire connecting the circuit
Clk_div_s #(.div_value(29999999)) ip5( .clk(clk), .divided_clk(dclk)); //run clock division command
Dflipflop A0 (j9, dclk, clr, Q[2], Qbar[2]); Dflipflop A1 (j10, dclk, clr, Q[1], Qbar[1]); Dflipflop A2 (~x, dclk, clr, Q[0], Qbar[0]); //Use the D Flip Flop command to link the inputs and //wires and G0 (j0, Q[2], Qbar[1]); and G1 (j1, Q[2], Qbar[1], ~x); and G2 (j2, Q[2], Q[0], x); and G3 (j3, Qbar[2], Q[1], Qbar[0], x); and G4 (j4, Qbar[2], Q[1], Q[0], ~x); //AND the variables according to transition eqn & circuit diag.
and G5 (j5, Q[1], Qbar[0], ~x); and G6 (j6, Q[1], Q[0], x); and G7 (j7, Qbar[1], Qbar[0], x); and G8 (j8, Qbar[1], Q[0], ~x); //AND the variables together according to transition eqn & circuit //diagram or G9 (j9, j0, j1, j2, j3, j4); or G10 (j10, j5, j6, j7, j8); //OR the variables together according to transition eqn & circuit //diagram
endmodule
module Dflipflop(input D, clk, reset, output reg Q, Qp); //coding D Flip Flop to be used above
always @(posedge clk or negedge reset) begin //operate when clock is 1 or reset is 0 if (~reset) begin //if reset = 0 Q<=0; //force Q=0 Qp<=1; end //force Q=1
else begin //if reset = 1 Q<=D; //set Q = D Qp<=~D; end //set Q = D* end endmodule
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