PLEASE DO NOT COPY AND PASTE OTHER ANSWERS FROM OTHER SITES. Computer Architecture  Assume the following information is gathered about a system: - 95% of all main memory accesses are found in the cache - 25% of references to the cache are writes - Each cache block is two words, and the whole block is read on any miss. - At any time, 30% of the blocks in the cache have been modified - The cache uses write allocate on a write miss - The bus reads or writes a single word at a time (the memory system can not read or write two words at once) - Write-back is used - Each cache hit takes 1 clock cycle - On average, the miss penalty is 52 clock cycles Question: Find the average number of main memory accesses per CPU reference to the cache. To find the average (weighted average), you need to find the number of accesses to memory on cache hits and cache misses and whether the block in cache has been modified (dirty). Therefore, there are 8 combinations as shown in the table below. I have filled out some (not sure if it is right). Please figure out the other rows. (See attached image)

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PLEASE DO NOT COPY AND PASTE OTHER ANSWERS FROM OTHER SITES.

Computer Architecture 

Assume the following information is gathered about a system:

- 95% of all main memory accesses are found in the cache

- 25% of references to the cache are writes

- Each cache block is two words, and the whole block is read on any miss.

- At any time, 30% of the blocks in the cache have been modified

- The cache uses write allocate on a write miss

- The bus reads or writes a single word at a time (the memory system can not read or write two words at once)

- Write-back is used

- Each cache hit takes 1 clock cycle

- On average, the miss penalty is 52 clock cycles

Question: Find the average number of main memory accesses per CPU reference to the cache. To find the average (weighted average), you need to find the number of accesses to memory on cache hits and cache misses and whether the block in cache has been modified (dirty). Therefore, there are 8 combinations as shown in the table below. I have filled out some (not sure if it is right). Please figure out the other rows. (See attached image)

 

Cache hit?
Yes
Yes
Yes
Yes
No
No
No
No
Access Type
Read
Read
Write
Write
Read
Read
Write
Write
Block dirty?
Y
Frequency
Memory accesses
95% * 75% * 30%
* 0 (because it is hit)
95% * 75%
*0
25%* 95%
*1
Y
N
N
5% * 75% * 70%
*2 (because of items c & f)
Y
75%* 5%
*2
N
Y
Total (Sum to get Avg. number of memory access per CPU access):
ZA
N
Avg. # of
memory
accesses
= 0
= 0
= 0.2375
= 0.052
= 0.0375 * 2
Transcribed Image Text:Cache hit? Yes Yes Yes Yes No No No No Access Type Read Read Write Write Read Read Write Write Block dirty? Y Frequency Memory accesses 95% * 75% * 30% * 0 (because it is hit) 95% * 75% *0 25%* 95% *1 Y N N 5% * 75% * 70% *2 (because of items c & f) Y 75%* 5% *2 N Y Total (Sum to get Avg. number of memory access per CPU access): ZA N Avg. # of memory accesses = 0 = 0 = 0.2375 = 0.052 = 0.0375 * 2
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