Please construct truth table and fill out circuit diagram for NAND based D latch. Circuit already constructed. thank you..

1. Implement the NOT, AND, and OR gates by using NAND gate only 2. Implement the NOT, AND, and OR gates by using NOR gate only 3. Give some applications for XOR, and NOR logic circuits.

1. A circuit containing two FET transistors is shown below. The values of Va and Vb can be either 5 V (digital 1) or OV (digital 0). Similar to what we did in class, draw a table that lists the four possible combinations of Va and Vb, and the corresponding output voltage Vout. Which digital logic gate does this correspond to (AND, NAND, OR, or NOR)? 5 V ww R 5 V Va Vout ww R FET 2. Repeat problem 1 for the circuit below. Vb Vout FET Va Vb LL FET1 FET2

4. The data sheet of a quad two-input NAND gate specifies the touiwing parameters: lon (max.)-0.4 mA, Von (min.) =2.7 V. Vn (min.) =2V, Vn. (max. 0.8 V, VoL (max.) 0.4 V, lot. (max.)8 mA. In (max.)-0.4 mA, Inn (max.)-201A, lecs (max.)1.6 mA, lce (max.)44 mA, tol ta15 ns and a supply voltage range of 5 V. Determine (a) The average power dissipation of a single NAND gate. (b) The maximum average propagation delay of a single gate, (e) The HIGH-state noise margin and (d) the LOW-state noise margin 5- Refer to exercise 4. How many NAND gate inputs can be driven from the output of a NAND gate of this type?