Consider the circuit below. A B C Gate Delay NOT 9 ns AND 13 ns OR 11 ns XOR 23 ns NAND 12 ns NOR 10 ns a) Calculate the critical path delay of the circuit. Use gate delays specified in the table. Also identify the critical path of circuit by its input, Gates, and output. b) Use Karnaugh map to simplify the circuit and re-calculate the critical path. c) Prepare Gate Level System Design of simplified circuit using CMOS technology.

Consider a digital logic circuit with two diodes as shownin figure 1. The diodes D1 and D2 are ideal (i.e. Vy = 0). 12 D ov, out 10 D2 5V 50kO Figure 1 A digital logic circuit with two ideal diodes A. Complete the equivalent circuit below and determine the output voltage vout oV and v, = 5V. Verify the conduction states of diodes by finding the current through D, and the voltage across D, when vị = Note that the output voltage is the same when v, = 5V and v, = 0V. 12 D out 12 D2 5V 50k2 Complete the equivalent circuit below and determine the output voltage vout when vị = v2 = В. 5V. 1Ω D Qut 10 5V 50k2 B.

1. Draw the static CMOS circuits for the following functions. Be sure to label power, ground, and output. a. Y = AB + C + DE b. Y (A + BC)(D + E) (note the bar: A, E) c. Y = A+ CD + E(A + B) (must use DeMorgan's)

Assume Vth = 1V and k = 50mA/V2. Given the schematic below, do the following:  1) Indicate and verify the state of each MOSFET and ?0 for the following input combinations. Fill-out the table below for each assumed state of the MOSFET for every input combination. Use ?ds,on approximation for linear operation. 2) Determine what kind of logic circuit is implemented in the circuit.