Consider the circuit below. A B C Gate Delay NOT 9 ns AND 13 ns OR 11 ns XOR 23 ns NAND 12 ns NOR 10 ns a) Calculate the critical path delay of the circuit. Use gate delays specified in the table. Also identify the critical path of circuit by its input, Gates, and output. b) Use Karnaugh map to simplify the circuit and re-calculate the critical path. c) Prepare Gate Level System Design of simplified circuit using CMOS technology.

Introductory Circuit Analysis (13th Edition)
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ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
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Consider the circuit below.
A
B
C
Gate
Delay
NOT
9 ns
AND
13 ns
OR
11 ns
XOR
23 ns
NAND
12 ns
NOR
10 ns
a) Calculate the critical path delay of the circuit. Use gate delays specified in the table. Also
identify the critical path of circuit by its input, Gates, and output.
b) Use Karnaugh map to simplify the circuit and re-calculate the critical path.
c) Prepare Gate Level System Design of simplified circuit using CMOS technology.
Transcribed Image Text:Consider the circuit below. A B C Gate Delay NOT 9 ns AND 13 ns OR 11 ns XOR 23 ns NAND 12 ns NOR 10 ns a) Calculate the critical path delay of the circuit. Use gate delays specified in the table. Also identify the critical path of circuit by its input, Gates, and output. b) Use Karnaugh map to simplify the circuit and re-calculate the critical path. c) Prepare Gate Level System Design of simplified circuit using CMOS technology.
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