+ نظیر ملک Q5 (12 Marks) Consider a four-input CMOS NOR logic gate. Draw the circuit, then. a) Determine the W/L ratios of the transistors to provide for symmetrical switching based on the CMOS inverter design with (W/L) 2 and (W/L)p=4. b) If the load capacitance of the NOR gate doubles, determine the required W/L ratios to provide the same switching speed as the logic gate in part (a).

Problem 3 Consider a CMOS static inverter. Please be careful with units. The NMOS transistor has the following characteristics. The channel length is 350 nanometers. For NMOS: tox=10nm, Vm=0.25V, un=560cm²/vsec, W=700nm, L=350nm For PMOS: tox=10nm, Vtp=-0.35V, up=240cm²/vsec, W=700nm, L=350nm Compute the resistance R₁ for NMOS if the power supply voltage (Vad) is 1.25 volts.

why the CMOS inverter circuit below contains two opposite- type MOSFET transistors (nMOS and pMOS)? and why called inverter circuit ?

a) A standard TTL inverter gate is shown in the figure. The supply voltage is 5V. Calculate the output voltage for both logic low and logic high input cases assuming input voltages respectively as 0.11V and 4.2V. Br= 130; BR = 0.24. You can make approximations when needed. Br = IcIs active region; BR = IE/ls inverse active region b) Assume you connect a resistor of 1.8K to the output of the circuit when the output is at logic high. What will be the change in the output voltage? 1302 R3 1.6k2 R, 4k2 Input o T, Output T, V, V. IkQ R,