Draw the schematic circuit for a resistively loaded NMOS inverter and the relative voltage transfer characteristic. Indicate on the graph the three different regions of operation of the transistor.

a) A standard TTL inverter gate is shown in the figure. The supply voltage is 5V. Calculate the output voltage for both logic low and logic high input cases assuming input voltages respectively as 0.11V and 4.2V. Br= 130; BR = 0.24. You can make approximations when needed. Br = IcIs active region; BR = IE/ls inverse active region b) Assume you connect a resistor of 1.8K to the output of the circuit when the output is at logic high. What will be the change in the output voltage? 1302 R3 1.6k2 R, 4k2 Input o T, Output T, V, V. IkQ R,

1) a) Design a depletion-mode load inverter shown in the below figure with Vpp = 3.3V, P = 0.25mW, VL = 0.2V, VTo = 0.6V for the switching transistor, VTo = -3V for the depletion- mode load, y = 0.5VV, and 2șF = 0.6V. b) What are the vlues of NML and NMµ? ML 0a 어 Ms