My exercise was to modify a testbench code to perform a full checking on the results produced by the 4-bit adders in both structural and behavioral models. Please help explain the below verilog testbench coding for 4-bit adder, the answer is from my friend but I don't understand. Please explain line by line why it is needed and how does the testbench function to test the adders that were wrote in verilog code. Codes are attached below for easier copy and paste you want to test in edaplayground. Please help, I really don't understand, everyone hates me, I am failing the class, I will rate you 5 stars I promise 4-Bit Adder Structural Module Testbench for Structural 4-Bit Adder Module module adder1(A, B, Cin, Sum, Cout); input [3:0] A,B; input Cin; output [3:0] Sum; output Cout; wire C0, C1, C2; fulladder M1(A[0], B[0], Cin, Sum[0], C0); fulladder M2(A[1], B[1], Cin, Sum[1], C1); fulladder M3(A[2], B[2], Cin, Sum[2], C2); fulladder M4(A[3], B[3], Cin, Sum[3], Cout); endmodule module fulladder(A, B, Cin, Sum, Cout); input A, B, Cin; output Sum, Cout; wire n1, n2, x1; xor u1 (x1, A, B); xor u2 (Sum, x1, Cin); and u3 (n1, Cin, x1); and u4 (n2, A, B); or u5 (Cout, n1, n2); endmodule `timescale 1us / 100ns //total duration 5.12ms module adder1_tb(); reg [3:0] A, B; reg Cin; wire [3:0] Sum; wire Cout; adder1 u1 (A, B, Cin, Sum, Cout); integer i; initial begin Cin=0; for (i=0; i<256; i=i+1) begin {B,A}=i; #10; end Cin=1; for (i=0; i<256; i=i+1) begin {B,A}=i; #10; end end endmodule 4-Bit Adder Behavioral Module Testbench for Behavioral 4-Bit Adder Module module adder2(A, B, Cin, Sum, Cout); input [3:0] A, B; input Cin; output [3:0] Sum; output Cout; assign {Cout, Sum} =A+B+{3'b0,Cin}; endmodule `timescale 1us / 100ns //total duration 5.12ms module adder2_tb(); reg [3:0] A, B; reg Cin; wire [3:0] Sum; wire Cout; adder2 u1 (A, B, Cin, Sum, Cout); integer i; initial begin Cin=0; for (i=0; i<256; i=i+1) begin {B,A}=i; #10; end Cin=1; for (i=0; i<256; i=i+1) begin {B,A}=i; #10; end end endmodule
My exercise was to modify a testbench code to perform a full checking on the results produced by the 4-bit adders in both structural and behavioral models. Please help explain the below verilog testbench coding for 4-bit adder, the answer is from my friend but I don't understand. Please explain line by line why it is needed and how does the testbench function to test the adders that were wrote in verilog code. Codes are attached below for easier copy and paste you want to test in edaplayground. Please help, I really don't understand, everyone hates me, I am failing the class, I will rate you 5 stars I promise
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4-Bit Adder Structural Module |
Testbench for Structural 4-Bit Adder Module |
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module adder1(A, B, Cin, Sum, Cout); input [3:0] A,B; input Cin; output [3:0] Sum; output Cout;
wire C0, C1, C2;
fulladder M1(A[0], B[0], Cin, Sum[0], C0); fulladder M2(A[1], B[1], Cin, Sum[1], C1); fulladder M3(A[2], B[2], Cin, Sum[2], C2); fulladder M4(A[3], B[3], Cin, Sum[3], Cout);
endmodule
module fulladder(A, B, Cin, Sum, Cout); input A, B, Cin; output Sum, Cout;
wire n1, n2, x1; xor u1 (x1, A, B); xor u2 (Sum, x1, Cin); and u3 (n1, Cin, x1); and u4 (n2, A, B); or u5 (Cout, n1, n2);
endmodule |
`timescale 1us / 100ns //total duration 5.12ms
module adder1_tb();
reg [3:0] A, B; reg Cin; wire [3:0] Sum; wire Cout;
adder1 u1 (A, B, Cin, Sum, Cout); integer i;
initial begin
Cin=0; for (i=0; i<256; i=i+1) begin {B,A}=i; #10; end
Cin=1; for (i=0; i<256; i=i+1) begin {B,A}=i; #10; end
end endmodule |
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4-Bit Adder Behavioral Module |
Testbench for Behavioral 4-Bit Adder Module |
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module adder2(A, B, Cin, Sum, Cout); input [3:0] A, B; input Cin; output [3:0] Sum; output Cout;
assign {Cout, Sum} =A+B+{3'b0,Cin};
endmodule |
`timescale 1us / 100ns //total duration 5.12ms
module adder2_tb();
reg [3:0] A, B; reg Cin; wire [3:0] Sum; wire Cout;
adder2 u1 (A, B, Cin, Sum, Cout); integer i;
initial begin
Cin=0; for (i=0; i<256; i=i+1) begin {B,A}=i; #10; end
Cin=1; for (i=0; i<256; i=i+1) begin {B,A}=i; #10; end
end endmodule |
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