Kleno As the clock pulses continue what two values will you see displayed on the 7-segment unit?

What is the period of a 2kHz signal?

Question 20 Choose the 8088 signals that are used to generate IOWR. ALE RD WR 1O/M IORD

1. A synchronous finite state machine contains a single 'Serial Data' input (SD) and two outputs (S and 7). Output S should be active for one clock pulse every time the input sequence 11010 is detected and output T should be active every time the input sequence 11001 is detected. The functionality of this machine may be partially represented by a timing diagram as shown in Figure 1. Clock a) SD S T Figure 1: Synchronous finite state machine timing diagram Derive the Moore model state diagram for this machine. Hint: ensure that the machine operates correctly even if the bit pattern is preceded by sub-sections of the pattern. [5]