KINGDOM OF SAUDI ARABIA iyageull ñyel ASlaall Ministry of Higher Education وزارة التعليم العالي King Khalid University College of Computer Science جامعة الملك خالد كلية علوم الحاسب الآلي KING KBALID UNIVERSITY Assignment1- Computer Organization The next table represents a truth table of a 1-bit comparator. With 3 outputs. A A>B AB B A

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الم ملكة العربية السعودية
وزارة التعليم العالي
KINGDOM OF SAUDI ARABIA
Ministry of Higher Education
King Khalid University
College of Computer Science
جامعة الملك خالد
كلية علوم الحاسب الآلي
KING KHALID UNIVERSITY
Assignment1- Computer Organization
The next table represents a truth table of a 1-bit comparator. With 3 outputs.
A
B
A>B
A<B
A=B
1
1
1
A-B
A
1-bit
A>B
Comparator
B
A<B
1. Design a module with Verilog for this circuit of the 3 outputs,
2. Make a testbench and simulate your circuit on a waveform.
NB: record a video showing the waveform. Send the video+ the code of
the module+ Simulation file+ code of the testbench
Dr. Olfa Ben said
o o
Transcribed Image Text:الم ملكة العربية السعودية وزارة التعليم العالي KINGDOM OF SAUDI ARABIA Ministry of Higher Education King Khalid University College of Computer Science جامعة الملك خالد كلية علوم الحاسب الآلي KING KHALID UNIVERSITY Assignment1- Computer Organization The next table represents a truth table of a 1-bit comparator. With 3 outputs. A B A>B A<B A=B 1 1 1 A-B A 1-bit A>B Comparator B A<B 1. Design a module with Verilog for this circuit of the 3 outputs, 2. Make a testbench and simulate your circuit on a waveform. NB: record a video showing the waveform. Send the video+ the code of the module+ Simulation file+ code of the testbench Dr. Olfa Ben said o o
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