Instructions Design the synchronous 3-bit binary down counter with D-lip-flops and any number of 2to1 multiplexers. Inverters can be used. The flip-flop outputs serve as outputs of the counter following the sequence 000-> 111-> 110-> 101->100->011->010->001- > ..and repeat from 000. The initial state is not critical. 1. Obtain the D-flip-flip input excitation equations 2. Implement the equations with any number of 2to1 multiplexers. Sketch the schematic.

a. Construct a synchronous 3-bit Up/Down counter with irregular sequence by using J-K flip-flops. The state diagram is shown below. Y = 1 00 010 110 Y =0 101 111 0, 011 100 001 b. Construct an asynchronous counter with a modulus of eleven by using J-K flip-flops. The counter should follow the straight binary sequence from 0000 through 1011. c. The counters are used in cascading in order to achieve the higher modulus operation. A certain application requires an overall modulus of 39,000 which can be achieved by placing the counters in cascading. You are requested to design a circuit for the said purpose by using 74HC161.

An equation in reduced SOP form, is F=AB+B'C+A'C'. I need to draw a logic circuit F using NOT/AND/OR  and  logoc circuit F using all NAND gates. Thank you for the help. I understood the previous types of gates but I am confused on how to draw these circuits.