In TSSST switch (where SSS stands for a three-stage space-division switch) with N=150.  It is used 15 time division switches in the first stage and 15 time division switches in the fifth stage. We use 3 crossbar switches in the second stage, 2 crossbars at the third stage, and 3 crossbars at the fourth stage. What is the total number of crosspoints?

Draw a circuit to implement a switching network with two data inputs (A and B), two data outputs (C and D), and a control input (S). If S=1, the network is in pass-through mode: C=A and D=B. If S=0, the network is in crossing mode: C=B, and D=A. Use the most reasonable combinational building blocks or gates. Label the inputs and outputs.

Use VHDL to implement a 16-to-1 Multiplexer. The inputs are w0, w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, and w11. The last four inputs are not attached to an input signal. How many select bits need the circuit?

Assume we are writing a testbench for a sequential circuit that has three control inputs (cA, cB, cC) and a periodic clock (clk). If we define CLK_PERIOD as a localparameter with a value of 50 (nsec), write the testbench segment that would ensure all possible combinations of the control inputs were tested on a clock rising edge. This is can be done more elegantly if you define each time step in terms of the constant CLK_PERIOD. Your answer should include the statements that define clk, cA, cB, and cC over time. Hint: think of how you would show all combinations of three variables on a truth table and replicate that over time, where each combination is held over a timespan with a clock triggering edge.

Design the interface for a positive logic switch to TM4C123GXL Port A pin 7. Show formulas and calculations for each circuit element. Draw the circuit schematics with components labelled with their names and values. Write the C code as a function to initialize the port for interfacing the switch. Write a function to read the data value of Port A pin 7. Comment your code to explain each initialization step clearly.

Embedded system

The following switching functions are to be implemented using a decoder. The minimum configuration of the decoder should be S-Em (1, 2. 4. 8, lo, 14) S-Em (2. 5, 9. 11) f,= Em (2, 4. 5, 6. 7) Select the correct response. 5 to 32 line O2 to 4 line 4 to 16 line O 3 to 8 line

A PWM signal is required for a motor controller. The PWM is generated by a TPM in a KL25Z. The signal for no motion of the motor is a 10 millisecond period with a 50% duty cycle. Which setup below is NOT a correct setup for a TPM for this starting condition? Ignore the "-1" adjustment for the counts. It is not important in this application. Clock: 3.2768 MHz Prescale: 64 Period: 512 Pulse Width: 256 Clock: 4 MHz Prescale: 4 Period: 10,000 Pulse Width: 5.000 Clock: 8 MHz Prescale: 2 Period: 20.000 Pulse Width: 10,000 Clock: 24 MHz Prescale: 16 Modulus: 15.000 Pulse Width: 7,500

1.1 Design a circuit for the traffic light unit in Multisim. The design should include 3 positive edge triggered D flip-flops. Set your clock signal to 1Hz. Please include Four screenshots of your working circuit, with each screenshot showing each of the light configurations shown in Figure 1. 000 100 010 110 001 Figure 1. A state diagram for a traffic light control The design should include 3 positive edge triggered D flip-flops. Use 1 flip-flop to control the on and off of a given light, and the state machine should switch from Red (100) -> Red and Amber (110) - > Green (001) -> Amber (010) and repeat the cycle again, with the following transition table: Current state Next state 000 100 100 110 110 001 001 010 010 100 ABC A*B*C* Table 1. A transition table for the traffic light unit

0 0 0 W 0 0 0 0 0 1 1 1 Complete the truth table for the circuit below. It has four inputs (w, x, y, z) and two outputs (C, S). In a given row, outputs for both S, C should be correct to get any credit. w x y z 1 X 0 0 0 0 1 1 1 1 0 0 0 0 y 0 0 1 1 0 0 1 1 0 0 1 1 I₁ DECODER Io 3 Z 0 1 0 1 0 1 0 1 0 1 0 1 2 MUX mui 3 Bº S FULL ADDER -S C