I need expert assistance in solving the choices, providing evidence not through explanations but through images or by illustrating with a diagram of the EMU8086 processor. -1. The Intel 8086 microprocessor can read/write 16 bit data from or to a. I/O device b. register (C, memory d. processor 2. Which unit in the 8086 microprocessor is responsible for pre-fetching instructions from memory? a. EU b. ALU c. BIU 3. The memory of 1M byte size could be divided into a. twenty-one b. thirty-four d. CU Kbyte segments. d. sixty-four c. thirty-three 4. Which of the following programming statements is NOT a valid comparison operator in Arduino? != (not equal to) b. < (less than) c. and (logical AND) d. = (equal to) 5. How many A/D converter inputs pins does port-E in the PIC16F877A? b. 6-Pins c. 4-Pins a. 3-Pins 6. How much the size of the program memory space in the b. 16Kx16 bits c. 8Kx14 bits a. 32Kx8 bits 8-Pins PIC16F877A microcontroller? d. 4Kx14 bits

Q2. (a) Figure 2 shows the pinout diagram (and their functional description) of the 2114 Static RAM memory IC. Using a neat sketch show how such IC may be interfaced with an M68000 microprocessor to realise a system that needs 1K x 16 bits of RAM. [Note: 2114 is a 4-bit memory IC. You will need multiple ICs to make up the 16-bit address bus of M68000 processor.] Ao-Ag Pin Names Address Inputs A6 1 A5 2 A4 AO 5 A16 A2 7 CS 8 GND 9 -23456782 18 Vcc WE Write Enable 17 A7 CS Chip Select 16 A8 1/0₁-1/04 Data Input/Output A3 4 15 A9 VCC Power (+5V) GND Ground 14 I/O 1 13 I/O 2 Truth Table 12 1/03 CS WE Comments 11 I/O 4 H X Chip Deselected L L Write 10 WE L H Read Figure 2 (b) Design an address decoder circuit to realise the following memory map (shown below in hexadecimal notation). The unused address range should generate an active low signal to be connected to the BERR* input of the M68000 microprocessor. Use the partial address decoding technique for your design. ROM1 00 0000 03 FFFF…

Q2. (a) Figure 2 shows the pinout diagram (and their functional description) of the 2114 Static RAM memory IC. Using a neat sketch show how such IC may be interfaced with an M68000 microprocessor to realise a system that needs 1K x 16 bits of RAM. [Note: 2114 is a 4-bit memory IC. You will need multiple ICs to make up the 16-bit address bus of M68000 processor.] Ao-Ag Pin Names Address Inputs A6 1 A5 2 A4 3 A3 4 AO 5 A1 6 A2 7 CS 8 GND 9 +23456700 18 Vcc WE Write Enable 17 A7 CS Chip Select 16 A8 1/01-1/04 Data Input/Output 15 A9 Vcc Power (+5V) GND Ground 14 I/O 1 13 I/O 2 Truth Table 12 1/03 CS WE Comments 11 1/04 Н Chip Deselected L L Write 10 WE L H Read Figure 2 (b) Design an address decoder circuit to realise the following memory map (shown below in hexadecimal notation). The unused address range should generate an active low signal to be connected to the BERR* input of the M68000 microprocessor. Use the partial address decoding technique for your design. ROM1 00 0000 03 FFFF…

Please may you give the solution to this computer science question! Thank you

I need the solution, expert, to be correct with clarification. a. Write an 8086-microprocessor program to perform the result of the logical expression: BP (X₁ X2) + (X₁. X2), where X₁-01FFH, X2=AD58H: b. There are 30 data bytes are stored in memory location with offset address 3100H to 311EH. Write 8086 microprocessor program to transfer the block of data to new location with offset address 4201H to 421F

Solve in 8086 microprocessor

Q1. (a) Design a stick (layout) diagram for the following static CMOS logic gate, where A, B, C, D are the logic gate inputs and O/P is the output: VDD D-d[Q8 A-Q5 B-Q6 C-d [Q7 O/P CQ3 DQ4 B-Q2 AQ1 Vss Figure 1 Use dual-well, CMOS technology. Include wells, well-taps, contact cuts, routing of power and GND in your diagram. Use colour coding and/or clear and readable detailed annotations to represent the wires in the different layers. (b) The logic gate from (a) needs to drive a capacitive load of 150 fF with a rise-time and fall-time of 1.2 ns. If the length of all transistors is 0.5 μm, calculate the required widths for all P-type and all N-type MOSFETs in the logic gate to achieve the required edge-speeds. Clearly show the calculation steps of your solution. Assume VDD = 5 V, K'n = 50 μA/V², K'p = 20 μA/V²

program using emu 8086

Q1. (a) Design a stick (layout) diagram for the following static CMOS logic gate, where A, B, C, D are the logic gate inputs and O/P is the output: VDD D-d[Q8 A-Q5 B-Q6 c-d[Q7 O/P CQ3 DQ4 B-Q2 A-Q1 Vss Figure 1 Use dual-well, CMOS technology. Include wells, well-taps, contact cuts, routing of power and GND in your diagram. Use colour coding and/or clear and readable detailed annotations to represent the wires in the different layers.

List and describe two AVR instructions. As part of your description make sure that you list the operation for each instruction that is provided in the instruction set summary.