How to handle Dirty Cache. Dirty Cache contains data that is different than main memory. This can create a serious problem, if there is more than one processor accessing main memory.

Explain the differences between a write-through cache change and a write-back cache modification, how they function in shared memory systems, and the advantages and disadvantages of utilizing either method.

A cache is organized as a 4 way set associative cache Each set's cache line consists of 4 words (meaning there are 16 bytes per line, for each set of the cache). Each set individually has one Valid bit, and one Dirty bit, for each line. The tag field of this cache is 8 bits wide. The address is 32 bits wide. Question 1a) What is the number of cache lines? Question 1b) What is the total number of 'memory bitcells' that are needed to design this cache (note, this includes the bitcells required for the tags, valid and dirty bits).

Explain the meaning of the terms "unified cache" and "Hadley cache."