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*How to compare the output waveform produced by both structural and behavioural models
*how to explain the waveform of both structural and behavioural models related to the coding
*how to explain both structural and behavioural models coding execute and work (add some comments)
Structural Module Model:
structural module code:
module adder1(A,B,Cin,Sum,Cout);
input [3:0] A, B;
input Cin;
output [3:0] Sum;
output Cout;
wire C0, C1, C2;
fulladder M1(A[0], B[0], Cin, Sum[0], C0);
fulladder M2(A[1], B[1], C0, Sum[1], C1);
fulladder M3(A[2], B[2], C1, Sum[2], C2);
fulladder M4(A[3], B[3], C2, Sum[3], Cout);
endmodule
module fulladder (A, B, Cin, Sum, Cout);
input A, B, Cin;
output Sum, Cout;
wire n1, n2 ,x1;
xor u1 (x1, A, B);
xor u2 (Sum, x1, Cin);
and u3(n1, Cin, x1);
and u4(n2, A, B);
or u5(Cout, n1, n2);
endmodule
Testbench code for structural module code:
module adder1_tb();
timeunit 1us;
timeprecision 100ns;
reg[3:0] A, B;
reg Cin;
reg[3:0] Sum;
reg Cout;
adder1 u1(A, B, Cin, Sum, Cout);
initial
begin
$dumpfile("dump.vcd");
$dumpvars(0, adder1_tb.u1);
A=4'b1010; B=4'b0101; Cin=0;
#10 A=4'b0011; B=4'b1101; Cin=1;
#10 A=4'b1111; B=4'b1111; Cin =0;
#10 $finish;
end
endmodule
behavioural module code:
module adder2(A, B, Cin, Sum, Cout);
input [3:0] A, B;
input Cin;
output [3:0] Sum;
output Cout;
assign {Cout, Sum} = A + B + {3'b0, Cin};
endmodule
Testbench for behavioural module code:
module adder2_tb();
timeunit 1us;
timeprecision 100ns;
reg [3:0] A, B;
reg Cin;
reg [3:0] Sum;
reg Cout;
adder2 u1(A, B, Cin, Sum, Cout);
initial
begin
$dumpfile("dump.vcd"); //To save the waveforms
$dumpvars(0, adder2_tb.u1); //To save the waveforms
A=4'b1010; B=4'b0101; Cin=0;
#10 A=4'b0011; B=4'b1101; Cin=1;
#10 A=4'b1111; B=4'b1111; Cin=0;
#10 $finish;
end
endmodule
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Step by stepSolved in 3 steps
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- MATLAB PROBLEMarrow_forwardDraw the logic diagram (synthesis output) using D F/F for the following HDL descriptions a evaluate the output values of b and c variables. (a) module blocking (clk,a,c); (b) module nonblocking (clk, a, c); input clk; input clk; input a; output c; input a; output c; wire clk: wire a: reg c; reg b; always @ (posedge clk ) begin b = a; c = b; end endmodule wire clk; wire a: reg c; reg b; always @ (posedge clk ) begin b <= a; c<= b; end endmodulearrow_forwardGoal AIM/OBJECTIVE (similar to the manual): This is an exercise in designing combinational circuits that can perform 4bit Full Adder and Half Adder. Write a Verilog Behaviour model program for 4bit Full Adder and Half Adder with truth table and circuit diagram.arrow_forward
- Draw the logic diagram of the digital circuit specified by the following Verilog description:arrow_forwardTask 4: Application of 7-Segment Display Controller: You are to design a combinational circuit that displays the 7-segment display outputs triggered by the following 2 input combinations. The block diagram of the required design is shown below. Combinational Circuit a) Complete the table below. Inputs Y 7-segments Output (small letter) a e 1 b) Plot the truth table entries in the K-map matrix and simplify. Y X X a = b = C= Y Y X X X d = e = f = g = c) Draw and build the combinational logic circuit below.arrow_forwardMATLAB CODES ONLYarrow_forward
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