How long will the following code take on a 5-stage MIPS pipeline with forwarding and appropriate NOPS (assume no reordering capabilities exist)? Provide a brief explanation. add R5, R5, R7 Iw R6, 100(R7) sub R7, R6, R8

2-Assume that individual stages of the Datapath have the following latencies: IF ID EX MEM 250ps 350ps 150ps 300ps Also, assume that instructions executed by the processor are broken down as follows: alu 45% beq 20% Iw 20% SW 15% WB 200ps • What is the clock cycle time in a pipelined and non-pipelined processor? • Assuming there are no stalls or hazards, what is the utilization of the data memory? • Assuming there are no stalls or hazards, what is the utilization of the write-register port of the "Registers" unit?

Ques 1: Consider a three stage pipeline with logic delays of 10ns, 20ns, 40ns for the three stages, respectively. Latch delay = 10ns. I am allowed to split any one of these three stages into two equal sized substages. Doing so, will make a four-stage pipeline. What is the maximum throughput (in MIPS) of this new pipeline?

Q4. Assume the following sequence of MIPS instructions is executed on MIPS processor that support forwarding. Identify all data hazards. Apply instructions reordering technique to eliminate data hazards. Iw $1, 100 ($2) addi $2, $1, 10 Iw $3, 200 ($2) ori $4, $3, 5 add $6, $4, $2 sw $10 300 ($2)