For a 16T x 4 DRAM, how few internal address lines are acceptable?

What addresses in the output portion of the datapath are mapped to the DSR and DDR respectively? O DSR: x3O0, DDR, x306 DSR: XFE00, DDR: XFE02 O DSR: XFE04, DDR: ×FE06 DSR: XFE02, DDR: XFE00 DSR: XFE06, DDR: XFE04

For a computer with 56-bit physical addresses and a 8-way set associative cache of 64 KB where each cache line has the capacity of holding 32 words. Assume the word size is 3 and the architecture is byte-addressable. Answer the questions below: a.How many bits are needed for tag, index, word offset, and byte offs. Show your derivations and assumptions. b.What are the start and end physical addresses, in hex as discussed in class, for cache line 300? Cache line count starts from 0. c.What is the total size, in KB, of this cache? d.What is the tag value, in hex, of address 0xABCDEF98765432?

Why do we need so many different addressing modes?