Find the ratio of hole mobility to electron mobility of a CMOS inverter given that the beta ratio of pull-up etwork to pulldown network is 1.5 (Assume that W/L ratio of pMOS is 3 times greater than that of nMOS and all other parameters are same for both)

2. Which of the following statements on NMOS, PMOS and CMOS is NOT correct? A. When voltage between gate and source is greater than threshold, the connection betweer drain and source is closed for NMOS. B. When voltage between gate and source is greater than threshold, the connection betweer drain and source is closed for PMOS. C. A CMOS can be composed of an NMOS and a PMOS. D. When the input for a CMOS is low, the output of it is high.

A full bridge inverter with RLC load having the following values: R=7.5 Ohms, L=12.5 mH, C=22 uF. The switching frequency is 500 Hz and the DC input voltage is 180V. The THD of the load current is equal to (consider up to the fifth harmonics): Select one: Oa. 8% O b. 12% O c. 6% d. 4%

J VDD RD - Vout You may have already noticed that the common source amplifier circuit is basically the same as the NMOS RTL inverter, just used for different purposes. The slope of the inverter VTC (Vout-Vin curve) is also the small- signal voltage gain of the common source amplifier. Assume VDD = 5V and Vin M₁ Vthn 0.7 V for the NMOS, use PSPICE to simulate the VTC (sweep from 0 to 5 V) of the common source amplifier for the following conditions: (a) Fix RD = 100 kN, L = 1 µm, W = 1 μm. Vary kn² = 20, 100, and 500 μА/V². (b) Fix kn' = 100 µA/V², R₁ = 100 kQ, L = 1 μm. Vary W = 1, 5, and 50 μm. (c) Fix kn' = 1 100 μA/V², L = 1 µm, W= 1 µm. Vary RD = 10 k2, 100 kQ, 1 MQ. Compare the slopes of the VTCs (which correspond to the voltage gains of the amplifiers) you obtained from the various conditions in a-c and explain your results.

..A CMOS Inverter using a Power Supply of 3.3 V and Channel length = 20 nm is built in a process with the following specification: NFET: Process Transconductance = 167 (µA/V²); Threshold voltage = 0.58 V Width= 6 µm PFET: Process Transconductance = 75 (µA/V²) ; Threshold voltage = - 0.63V ; Width = 11 µm %3D a) Calculate Device Transconductances of the nFET and the pFET. b) Estimate the Midpoint voltage of the Inverter.

Sketch a 3-input NOR gate with transistor widths chosen to achieve effective rise and fall resistance equal to that of a unit inverter (R). Annotate the gate with its gate and diffusion capacitance's. Assume all diffusion nodes are contacted. Then sketch equivalent circuits for the worst case falling output transition and for the rising output transition.