2/ Consider CMOS inverter biased at VOD = 8v a with transistor parameters of KN = Kp and VTN = - VTP =lv Determine the critical voltages on the voltage transfer curve of a CMOS inverter.

J VDD RD - Vout You may have already noticed that the common source amplifier circuit is basically the same as the NMOS RTL inverter, just used for different purposes. The slope of the inverter VTC (Vout-Vin curve) is also the small- signal voltage gain of the common source amplifier. Assume VDD = 5V and Vin M₁ Vthn 0.7 V for the NMOS, use PSPICE to simulate the VTC (sweep from 0 to 5 V) of the common source amplifier for the following conditions: (a) Fix RD = 100 kN, L = 1 µm, W = 1 μm. Vary kn² = 20, 100, and 500 μА/V². (b) Fix kn' = 100 µA/V², R₁ = 100 kQ, L = 1 μm. Vary W = 1, 5, and 50 μm. (c) Fix kn' = 1 100 μA/V², L = 1 µm, W= 1 µm. Vary RD = 10 k2, 100 kQ, 1 MQ. Compare the slopes of the VTCs (which correspond to the voltage gains of the amplifiers) you obtained from the various conditions in a-c and explain your results.

6. What are nMOS and pMOS transistors? Why a positive voltage applied at the gate of the nMOS transistor while a negative voltage is applied at the gate of a pMOS transistor to make it work?

The NMOS and PMOS transistors have the following characteristics. The channel length is 350 nanometers. For NMOS: tox=50nm, Vtn-0.25V, un-560cm²/vsec, W=700nm, L=350nm For PMOS: tox-50nm, Vtp=-0.35V, up-240cm²/vsec, W=700nm, L=350nm a) Compute the NMOS gate capacitance CG in Femto Farads. b) Compute the resistance Rp for PMOS if the power supply voltage (Vdd) is 3.3 volts and the threshold voltage is 0.35 volts. Use the multiplying adjustment factor as 2.5.

Q3 Design parallel inverter to generate s mmzmmummm resistive load 120W,240Y, if the batiery voltage is 12V,