Fill in the timing diagram for a falling-edge-triggered S-R flip-flop. Assume Q begins at 0. L Clock S R e 4

The logic diagram on the right shows a "T-D flip- flop" that can function as a T-type flip-flop or a D-type flip-flop. i) Derive the next state equation for the T-D flip flop circuits. ii) Implement the circuit using D-type flip-flop as your memory element. iii) Implement your circuit using R-S flip-flop. Clock C(CONTROL) M (MODE) T_D LATCH K 2 2 b QBAR