Execution sequence of instructions in a pipelined processor can be visualized using a space-time diagram. Consider a processor having 4 stages and let there be 2 instructions to be executed. We can visualize the execution sequence through the space-time diagrams of “Non-overlapped execution” and “overlapped execution”.

A systolic array, which is a kind of array, is an example of a MISD machine. A systolic array is a pipeline network or "wavefront" of data processing units structured as a network. Because execution is triggered by the reception of fresh data, none of these components need the usage of a program counter. Each unit in a clocked systolic array computes in "lock-step," with each unit completing alternate calculation and communication phases in a single clock cycle.

An example of a MISD machine might be something like a systolic array, which is a kind of array. A pipeline network or "wavefront" of data processing units that is organised as a network might be referred to as a systolic array. Since the receipt of new data is what initiates execution, none of these components need the employment of a program counter in order to function properly. Each individual unit in a timed systolic array computes in "lock-step," meaning that within the course of a single clock cycle, each individual unit finishes alternating stages of computation and communication.

Consider a CPU that implements a single instruction fetch–decode–execute–write- back pipeline for scalar processing. The execution unit of this pipeline assumes that the execution stage requires one step. Describe, and show in diagram form, what happens when an instruction that requires one execution step follows one that requires four execution steps.