edge and other abrupt and gradual information of grayscale. can effectively eliminate the salt-and-pepper _and pass_ 15. Image derivative information, 16. noise. 17. Low-pass filtering method attenuates _, so as to achieve image smoothing.
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- 19) Consider a 6-bit ADC and full scale voltage measurement range of (0-59).The Resolution will be _________. 0.30 0.06 0.92 1.00Choose the correct answer low HDOP (Horizontal Dilution of Precision) number such as2 indicates a ........................... a.poor fix b.good fix c.poor signal quality d. good signal qualityDecoder circuit as shown in the following Figure. if A is LSB and C is MSB, the output expression F= YO Y Y, Y, D. Y. Decoder O a. B' O b. C O'c.B O d. C
- Make a signal flow diagram out of the data. Label everything properly.b. Explain how to decide the sampling rate for a multi-frequency input signal. c. An ADC with word length of 24 bits. If the input analogue signal range is 3.7 V, what is the resolution of this ADC? d. Consider a thermocouple giving an output of 0.5 mVrc. What will be the word length required when its output passes through an ADC if temperatures from 0°C to 120°C are to be measured with resolution of 1.5°C?. Assume 12V as system voltage.We want to design a digital circuit that converts Gray code (ABC) to Binary code (xyz). Set up a 8-to- 1 line multiplexer so that the output gives y as a function of ABC. "A" is given to the most significant bit of the control inputs of the multiplexer. "C" is given to the least significant bit of the control inputs of the multiplexer.
- Exampic Bandwidth of the input to pulse code modulator is restricted to 4 kHz. The input varies from -3.8V to 3.8 V and has the average power of 30 mW, the required signal to quantization noise power ratio is 20 dB. The modulator produces binary output. Assume uniform quantization Calculate the number of bits required per sample.To implement a Full Subtracter, Using TWO 8:1 Multiplexers (ONE for Sum output and ONE for Cout output). Assign (or Connect) X, Y,and Bin variables to the Select Inputs of Multiplexers and connect 1 or 0 to each Data Input.What do you mean by fractional sampling rate conversion? Explain with an example of converting 48 kHz signal to 44.1 kHz signal using multi-stage fractional sampling rate converter. (ii) What are the effects of finite word length in digital filters
- What is a JFET? Explain its construction and describe the biasing methods available for biasing a JFET? Please don't write on paper3. Some GPS receivers use 1 bit ADCS (Analog-to-digital Converters) to sample and quantize the signal i.e. the output of the ADC is simply 2 quantization levels: -1 or +1. This is typically done to save on power. (a) What is the quantization SNR? How does it compare to typical thermal noise SNR of a GPS signal before correlating with the CDMA code? (b) Justify, how come it is possible to sample the signal using a single bit and still get good performance.Design an encoding matrix with diodes and resistors to display a decimal number to on the seven-segment display. You have 10 switches (WO-W9) with one terminal connected to Vec. For decimal number 0, switch 0 (S0) is closed, for decimal number 1, switch 1 (S1) is closed etc. (Switches are on the vertical axis, S0 on top and the outputs are taken on the horizontal axis (Y0-Y6), with “a" on the left and "g" on the right. Note that (Y0-Y6) outputs are used as inputs to seven-segment display. Since these outputs cannot drive the seven segment display LEDS you may need additional bipolar transistors and resistors. The supply voltage is 5V and each LED needs a current of 20mA. Note that this is a design problem and the design is not unique. Do your best! f a a e