(e) If both input is low of OR gate the output is (High, Low).

This circuit's modulator function is performed by the AND gate, which is a novel feature. A demodulator that matches the modulator is part of the receiver. Name a different widely used system that employs modulator/demodulator pairs or combinations.

Vcc NPN Small bias Vou |T2 PNP The top transistor T1 is closely matched to T2. What is the voltage at vout when vin is off? (Use KVL!) O VCC/2 O VCC O 1.4

For the device shown below: If the enable signal /EN (ENbar) is HIGH or (inactive) D So S1. EN O ALL outputs will be HIGH Except /YO (YObar) All the outputs will be HIGH All output will be HIGH except/Y3 (Y3bar) All the outputs will be LOW

3 DECIMAL PLACES ONLY

Q#02: Using Verilog gate level primitives, develop and verify a structural model for the circuit shown in figure. Use the following name for your testbench, the model, and its ports: _Combo_str (), Combo_str (Y, A, B, C, D). Exhaustively simulate the circuit and provide the graphical output demonstrating that the model is correct. For displaying the output results, consider using the $monitor and $display tasks. A B. D-

An analog output voltage for the input 1001 to a 4 bit D/A converter for all possible inputs assuming the proportionality factor K=1 will be (A) 9 (B) 6 (C) 3 (D) 1