Draw an ASM chart for a 2-bit binary counter having enable line E such that: E1 (counting enabled) E = 0 (hold present count).

Question [5]: Design a 3-bit synchronous counter which counts according to the following sequence 001 ® 110 ® 010 ® 101 ® 000 ® 111 and repeats. Design the counter using Two D-FF and One JK-FF such that the JK is the middle flip flop. What is the next count if the counter started with 011 (unused state)?

Generate a parameterized and portable Verilog model of an 8-bit ring counter whosemovement is from its MSB to its LSB.?

Write in RTL Verilog. Use a 4-bit RCA, four 2-1 MUX, and four D-type flip-flops to implement a 4-bit counter

Design a signed n-bit multiplier.

Draw a circular diagram for a 2 bit comparator .

Which of the following set of components is required for an n-bit full subtractor? a.) n full adders and nx1 MUX b.) nx1 MUX c.) nx1 MUX and n 1x2 decoders d.) n full adders, n 2x1 MUX, n not gates e.) n 2x2 decoders

4 bit 2’s Complement Multiplier INPUT A: 4 bit 2’s Complement numberINPUT B: 4 bit 2’s Complement numberOUTPUT: the product of A x B represented as a 8 bit 2’s Complement number   Do this:Build a 4 Bit UNSIGNED Multiplier as a subcircuit named UnsignedMultiplier use AND gate ,full and half adders for the circuit

Q3

Write a structural program for an excess-3 binary decoder