Draw a synchronous counter that will output a 10-kHz signal when a 1-MHz clock is applied.

1. Refer to given pic: What is the peak voltage of the clock pulse waveform and what is the Period & Frequency of the clock pulse waveform?

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Draw the 555 timer circuit that produces a square wave signal with Thigh=2ms and Tlow=1ms by calculating the resistor and capacitor values.

What is the period of a 2kHz signal?

Question 3 The 555 timer is connected in the following circuit. The resistance of the extra resistor is 102, the capacitance of the extra capacitor is 0.1F. The voltage input at Pin2 is Vcc. What is the output state at Pin3? 1) 2) Decide the voltage input value at Pin 6 when the condition is stable. 3) Decide the output state at Pin3 when a trigger input is applied at Pin2 (voltage input at Pin2 changes from Vcc to 0, and return back to Vcc immediately). 4) After the trigger input is applied at Pin2, how long would the output maintain at the unstable state. Vc R O Output Vo 555 Vc 0.01µF Trigger Input

Which statement out of the 5 is TRUE, Explain Why (50 Words) Pulse width modulation (PWM) can be used to control the speed of a DC motor. Whichstatement is correct?1. The ratio of the ON-times (supply voltage) and OFF-times (zero volt) send to theterminals of a DC motor is proportional to the average of the motor acceleration.2. PWM can be used to modulate the magnetic width of a brush-less AC motor.3. PWM modifies the pulses sent to a motor which in turn adjust the motor torqueproportionally to the pulse ratio.4. PWM can be used to adjust the average voltage delivered by a power source.This is achieved by rapidly switching the power signal on and off. Longer on-timescompared to the off times leads to a higher average power seen by the load, e.g., aDC motor.

1. A synchronous finite state machine contains a single 'Serial Data' input (SD) and two outputs (S and 7). Output S should be active for one clock pulse every time the input sequence 11010 is detected and output T should be active every time the input sequence 11001 is detected. The functionality of this machine may be partially represented by a timing diagram as shown in Figure 1. Clock a) SD S T Figure 1: Synchronous finite state machine timing diagram Derive the Moore model state diagram for this machine. Hint: ensure that the machine operates correctly even if the bit pattern is preceded by sub-sections of the pattern. [5]