Draw a Block Diagram of a 4-Bit Binary Adder Using Full Adders:   Design a Full Adder Using Only NOR Gates:

1. Implement the function below using only 2-input NAND gates. H(A, B, C, D, E) = ABCE + AB + AC + AD + CDE

Draw a full-adder using only NAND gates.

Draw a NAND gate implementation for F=AB+CD   Draw the circuit diagram of a 3-bit even-parity generator using XOR gates.

Design of a one-bit full-adder: 1). Draw the truth table (ABCin=000~111) of a one-bit full adder. 2). Based on truth table, draw the Karnaugh maps for Cout and Sum separately, find the simplified Boolean equations for Cout and Sum. 3). Sketch the gate level design of the circuit based on the Boolean equations you obtained. 4). Using Shannon’s expansion theorem, expand both Cout and Sum with respect to Cin. List your equations of Shannon expansion for Cout and Sum. Based on Shannon’s expansion, implement the full adder (Both Cout and Sum) with 2-to-1 MUX (using Cin as selection bit). Sketch your MUX-based design.

Draw a half-adder using only NAND gates.

Show the truth table of 4-bit adder and 4-bit adder cum subtractor.

Draw a circuit diagram of 4 bit full adder and full subtractor.

3- Use NAND gate, NOR gate, or combinations of both to implement the following expression:- a) X=A [B+C (D +E)] b) X = B (CDE + EF G) (A B + C)

You are given a 4-bit a comparator IC (7485). You have to verify the truth table for 4-bit comparator