Determine IDQ and VGSQ for voltage divider bias configuration for the JFET using graphical analysis. In addition to obtaining the VD, VS and VDS. We have the following data of the different elements of the circuit, such as: R1 = 3.3 MΩ, R2 = 3.3 MΩ, RD = 860 Ω, RS = 2.2 kΩ and powered by one source 12 volts. The manufacturer's sheet indicates that IDSS = 12 mA and VP = −3 V. Include the transfer characteristic graph to obtain the values ​​of the point Q.

Determine I_DQ and V_GSQ for voltage divider bias configuration
for the JFET using graphical analysis. In addition to obtaining the V_D, V_S
and V_DS.
We have the following data of the different elements of the circuit, such as:
R1 = 3.3 MΩ, R2 = 3.3 MΩ, RD = 860 Ω, RS = 2.2 kΩ and powered by one source 12 volts. The manufacturer's sheet indicates that I_DSS = 12 mA and V_P = −3 V. Include the transfer characteristic graph to obtain the values ​​of the
point Q.