Design the memory mapping between the Cache memory of 2 MB to the main memory of 4 GB using 4 way set associative method where the block or page or frame size is of 2 KB. Consider each memory location is byte addressable. Write the number of bits required for memory address, tag address, block address and block location.

Comparison of electrical circuits between DDR2 and DDR3 memory ?

How many address lines are required for accessing the data in the 8K bytes RAM memory chips. While the data is organized as bytes in the first two cases and as nibbles in the last cases?

a) 16 pieces of 32Kx8 SRAM are connected to 8088 to address the 00000H-7FFFFH memory region. This circuit uses 3 separate decoders to select the appropriate memory regions. Draw this circuit showing the address, data and control connections. (Do not buffering.) b) 8 pieces of 32Kx8 SRAM will be connected to the circuit in a way to form the address space C0000H-FFFFFH. Accordingly, draw the new circuit to be added to the above circuit. (You can use additional decoder or gate circuit.)

Q1) Write an assembly program to duplicate each memory location block (size N) starting at address 200h.

Answer the below questions. a. What is the counting range in binary and decimal for an up-counter with 3 bits? b. What is the counting range in binary and decimal for a down-counter with 4 bits?

Question 4 a) Show the output waveform of a NAND gate with the inputs A, B, and C indicated in the figure below. A C b) A cache has been designed such that it has 1024 lines, with each line or block containing 8 words. Determine the line number, tag, and word position for the 20-bit address 3E9D216 using the direct mapping method. c) The table below represents 10 lines from a 256 line cache that uses direct mapping with a block size of 4 words. Identify the address of the shaded data (8C16). 3 Line# |Tag Word 00 Word 01 Word 10 Word 11 10 110101 12 34 56 78 01010154 l000111 29 32 6A D3 8C A2 BC 12 ED F3 3 001100 33 2C C8 14 110011 9A D8 FO

Question: Assume a system comprises 16 GB physical memory with B KB page/frame sie and the instruction set comprises instructions that may need access to one (RET). two (PUSH AL or three (MOV A, B) memory locations to fetch the opcode and operands. Assuming that the system is configured with virtual memory: (a) What is the MINIMUM number of memory frames that must be allocated to a process running in the system? (b) What is the MAXIMUM number of memory frames that can be allocated to a process running in the system?

1- Identify the addressing mode for: MOV Cx, [SI] 2- The instruction that adds immediate datalcontents of memory location specified in an instruction/register to the contents of another register/memory location is a. SUB b. ADD c. MUL Share Content Participants

Final Exam EECE 32... moodle1.du.edu.om Question 16 Not yet answered Marked out of 2.0 P Flag question What characteristic of RAM memory makes it not suitable for permanent storage? Select one: a. None b. slow speed c. unreliable d. it is volatile e. small size Previous page Next page II