Consider two different implementations of the same instruction set architecture. Th e instructions can be divided into four classes according to their CPI (class A, B, C, and D). P1 with a clock rate of 2.5 GHz and CPIs of 1, 2, 3, and 3, and P2 with a clock rate of 3 GHz and CPIs of 2, 2, 2, and 2. Given a program with a dynamic instruction count of 1.0E6 instructions divided into classes as follows: 10% class A, 20% class B, 50% class C, and 20% class D, which implementation is faster? a. What is the global CPI for each implementation? b. Find the clock cycles required in both cases.

Add control states to the following to implement an exchange-with-memory instruction, xchg. such that xchg $rt,immed($rs) acts rather like the combination of a MIPS lw and sw: the result should be as if a sequence like t=memory[immed+rs]; memory[immed+rs]=rt; rt=t; where t is a temporary register. In case you were wondering why one would ever want to do this, it's actually a very common operation for synchronizing between concurrently executing processes using sempahores... but MIPS doesn't happen to do it this way, so it's also not a MIPS instruction. You're probably wondering where the t register is. Well, pick one you're not using... perhaps y (although you have to be careful about when you compute immed+rs for that to work). You should use the encoding suggested by the when below, so an instruction like xchg $9,4($10) would be encoded as op(3)+rt(9)+rs(10)+immed(4). when (op()) (op(3)) XchgStart: PCout, MARin, MEMread, Yin CONST(4), ALUadd, Zin, UNTILmfc MDRout, IRin Zout, PCin,…

Consider two different implementations, M1 and M2, of the same instruction set. There are three classes of instructions (A, B, and C) in the instruction set. M1 has a clock rate of 2.0GHz and M2 has a clock rate of 2.5GHz. The average number of cycles for each instruction class and their frequencies (for a typical program) are as follow on the table.  (a) Calculate the average CPI for each machine, M1, and M2.(b) Calculate the average MIPS ratings for each machine, M1 and M2