Consider the execution of the following code using the 5-stage pipelined MIPS with static branch predictor and early branch determination: sub $t1,$0, $0 beq $t1, $0, Else lw $t2, 0($s0) lw $t3, 0($t2) Else: lw $t4, 8($t2) sw $t5, 0($t4)

Q:..

The following sequence of MIPS instructions is processed using a 5-stage pipeline, as discussed in class. What is the minimum number of clock cycles are required, from start to finish? Assume that, if necessary, only pipeline stalls (not data forwarding) can be used to prevent data hazards.        lw   $1,0($2)     addi $3,$3,1     add  $2,$1,$1     add  $5,$4,$4