Consider the design of a CMOS compound gate computing F = AB + C           a) sketch the transistor level schematic b) sketch a stick diagram c) estimate the width, height and area from the stick diagram, for a 32nm process.

3. From an old quiz. Regions of operation are very important in circuit design using MOSFETS. Extracted from an old quiz. bias conditions, state whether the FET is operating in the OHMIC (TRIODE) region, SATURATION region, or CUTOFF region. Explain your reasoning. For the indicated Assume that |VT | 2 volts for both the NMOS and PMOS enhancement mode transistors. M1 M2 M3 М4 M5 M6 M1 M2 M3 VGS +3 & VDS +6 vGS = +1 & VDS = +8 VGS =-1 & VDS = -6 M4 M5 VGS = +6 & VDS = +2 VGS = -3 & VDS = -6 VGS = -3 & VDS = +6

Question Vvv  Draw the layout of this circuit using the conditions given. 1. (W/L)pmos = 2(W/L)nmos 2. one contact for each 3. overlay margin is Lambda.....

Follow the instructions below using the parameters below. 0.6um technology. Any size transistor (W or L) must be divisible by 0.3um to be produced by any company. Always set the sizes of W and L assuming the smallest L possible for each transistor according to the technology. Include units VDD = 3V: VT0P = 0.7V; VTON = 0.5V; unCox = 99uA / V ^ 2 upCox = 33uA / V ^ 2; gamma = 0.1 sqrt (V); 2ΦF = 0.6V Design a bit of a static RAM memory when the capacitance of Q, CQ = 5fF and the capacitance of the line bit is 1pF. a.  Draw your schematic identify each node and list the transistors. b. Draw the sense amplifier circuit and the precharge-equalizer, if the user wants to precharge the line to VDD. c. The access transistors in a RAM memory bit have a size (W / L) a = 6um / 0.6um Determines the minimum size of the NMOS transistors in the inverters. Justify the size you are choosing for each transistor