Consider an unpipelined processor. Assume that it has 1-ns clock cycle and that it uses 4 cycles for ALU operations, and 5 cycles for branches, and 4 cycles for memory operations. Assume that the relative frequencies of these operations are60%,20%, and20%respectively. Suppose that due to clock skew set up, pipelining the processor adds0.2 nsof overhead to the clock. Ignoring any latency impact, how much speed up in the instruction execution rate will we gain from a pipeline?

Consider an unpipelined processor. Assume that it has 1-ns clock cycle and that it uses 4 cycles for ALU operations, and 5 cycles for branches, and 4 cycles for memory operations. Assume that the relative frequencies of these operations are60%,20%, and20%respectively. Suppose that due to clock skew set up, pipelining the processor adds0.2 nsof overhead to the clock. Ignoring any latency impact, how much speed up in the instruction execution rate will we gain from a pipeline?    

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