Consider an OAI321 static CMOS gate. (a) Draw the logic diagram (i.e. using AND/OR/INVERTER gates) (b) Draw the transistor schematic (using NFET/PFETs)

Figure Q7 describes a Linear Feedback Shift Register (LFSR). Draw the equivalent schematic diagram of the system based on an off-the-shelf shift register, clearly showing the number of exclusive-OR gates needed to construct it. LIBRARY ieee; USE ieee.std logic_1164.all; entity lfsr is CLK, RESET: in STD LOGIC; Q: out STD LOGIC_VECTOR (5 downto 0) ); port ( end lfsr; architecture behavior of lfsr is begin process (CLK,RESET) begin if RESET='1' then Q <= "000001"; else Q <= ( Q(3) xor Q(2) xor Q(0) ) & Q(5 downto 1); end if; end process; end behavior;

Show the instantaneous descriptions for the acceptance of aabbbb by the pda in the image.

Design a Full Adder Circuit and provide its Gate-Level Modeling, Data Flow Modeling, and Behavioral Modeling.