Check whether the system descrībed by yn=x*n+x[n] is linear, time invariant, causal, stable and memory less

Draw the schematic of a modulo-6 syncrhonous counter (counting sequence is 010, 110, ...). The counter has the following features: Asynchronous Reset is Active High A value D can be loaded into the counter, using the Load signal, which is Active Low.

6. Which of the following is not a type of signal is... a. analog signalb. Chain signalc. Binary signald. Dict signale. digital signal

2. What are the basic five stages of the RISC pipeline, and explain the functions of each stage